Question about contassigns

[parag]

module M;
wire w, x;
reg r;
assign x = r;
assign w = x;

I have been working on verilog for some time now but I have a doubt
cont assigns and how it maps in hardware
Here ever though we have a contassign from x to w
does nt it mean that in hardware they are plain ly connected ,
so even a value change in w should be reflected in x isnit ?

Arent cont assigns not syhthesized?

 

[gabor]

On Oct 26, 12:27 am, parag <parag.p...@gmail.com> wrote:

module M;
        wire w, x;
        reg r;
        assign x = r;
        assign w = x;

I have been working on verilog for some time now but I have a doubt
cont assigns and how it maps in hardware
Here ever though we have a contassign from x to w
does nt it mean that in hardware they are plain ly connected ,
so even a value change in w should be reflected in x isnit ?

Arent cont assigns not syhthesized?

Synthesis normally treats this sort of assignment as a re-name.
i.e. after synthesis you will find a net called "w" and no nets
"r" or "x". If there was some other logic in the assignment like
assign w = x | b;
then you'd clearly have both nets "x" and "w" after synthesis.

In your case the reg "r" would be the only driver of the net,
so I don't see how "a change in w" could be inferred other than
a change in "r" which after synthesis is the same net. When
using continuous assigns for bidirectional signals, the
assignment clearly only drives in one direction, and in
this case often causes inference of a buffer, so in effect
assign w = x;
would not infer any path where changes in "w" cause a change
in "x".

Regards,
Gabor

 

[Michael]

On Oct 26, 11:32 pm, gabor <ga...@alacron.com> wrote:

On Oct 26, 12:27 am, parag <parag.p...@gmail.com> wrote:

module M;
        wire w, x;
        reg r;
        assign x = r;
        assign w = x;

I have been working on verilog for some time now but I have a doubt
cont assigns and how it maps in hardware
Here ever though we have a contassign from x to w
does nt it mean that in hardware they are plain ly connected ,
so even a value change in w should be reflected in x isnit ?

Arent cont assigns not syhthesized?

Synthesis normally treats this sort of assignment as a re-name.
i.e. after synthesis you will find a net called "w" and no nets
"r" or "x".  If there was some other logic in the assignment like
assign w = x | b;
then you'd clearly have both nets "x" and "w" after synthesis.

In your case the reg "r" would be the only driver of the net,
so I don't see how "a change in w" could be inferred other than
a change in "r" which after synthesis is the same net.  When
using continuous assigns for bidirectional signals, the
assignment clearly only drives in one direction, and in
this case often causes inference of a buffer, so in effect
assign w = x;
would not infer any path where changes in "w" cause a change
in "x".

Regards,
Gabor

I would say only "r" stays. Especially if "r" is a FF.

 

[gabor]

On Oct 28, 4:42 am, Michael <michae...@gmail.com> wrote:

On Oct 26, 11:32 pm, gabor <ga...@alacron.com> wrote:



On Oct 26, 12:27 am, parag <parag.p...@gmail.com> wrote:

module M;
        wire w, x;
        reg r;
        assign x = r;
        assign w = x;

I have been working on verilog for some time now but I have a doubt
cont assigns and how it maps in hardware
Here ever though we have a contassign from x to w
does nt it mean that in hardware they are plain ly connected ,
so even a value change in w should be reflected in x isnit ?

Arent cont assigns not syhthesized?

Synthesis normally treats this sort of assignment as a re-name.
i.e. after synthesis you will find a net called "w" and no nets
"r" or "x".  If there was some other logic in the assignment like
assign w = x | b;
then you'd clearly have both nets "x" and "w" after synthesis.

In your case the reg "r" would be the only driver of the net,
so I don't see how "a change in w" could be inferred other than
a change in "r" which after synthesis is the same net.  When
using continuous assigns for bidirectional signals, the
assignment clearly only drives in one direction, and in
this case often causes inference of a buffer, so in effect
assign w = x;
would not infer any path where changes in "w" cause a change
in "x".

Regards,
Gabor

I would say only "r" stays. Especially if "r" is a FF.

That's really up to the synthesis tool. For simulation all
nets would remain. For tools like XST I've found a tendency to
use the name of the last assigned net for some cases. I've
also seen cases where the translated design kept the net
name from a lower level module even though the module port
was brought to the top level of the design. The sad fact is
that it's often hard to find your nets after translation when
poring through the floorplanner or FPGA editor.

Regards,
Gabor