Question about conditional assignment

R

Rebecca

Guest
Hello, all

I want to implement the following logic
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;
Because C_ControlBits-1 will become -1 when C_ControlBits=0.
C_ControlBits is declared as constant in my design. But what's the
synthesizable VHDL code for this? I tried to put it into process but
failed.

Thanks for any hints,
Rebecca
 
Rebecca,
I would have to see more code to make a reasonable guess, so
instead I will make a blind guess. Often in a process
I find it handy to first initialize the entire array to
0 and then later over-write only the bits I need to set.

In this situation I would replace the conditional code
with:
Addr <= (others=>'0');
Addr(C_ControlBits+3 downto C_ControlBits) <= "1111" ;


Cheers,
Jim

Hello, all

I want to implement the following logic
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;
Because C_ControlBits-1 will become -1 when C_ControlBits=0.
C_ControlBits is declared as constant in my design. But what's the
synthesizable VHDL code for this? I tried to put it into process but
failed.

Thanks for any hints,
Rebecca
Click to expand...
 
On 23 Mar 2007 10:34:22 -0700, "Rebecca" <pang.dudu.pang@hotmail.com>
wrote:

Hello, all

I want to implement the following logic
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;
Because C_ControlBits-1 will become -1 when C_ControlBits=0.
C_ControlBits is declared as constant in my design. But what's the
synthesizable VHDL code for this? I tried to put it into process but
failed.

Thanks for any hints,
Click to expand...
Another wild guess...
look at "if ... generate" and "for ... generate"

- Brian
 
Jim:

I want to implement this
Addr(15 downto C_controlBits) <= SignalB;
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;



And your suggestion is what I can use.
But is that a good idear to overwite it? I know it is handy, but would
it cause problem for syncrounous design because it induces extra delay/
unstable phases and then probably data hazard?

Thanks,
Hongyan
 
Sorry I didn't describe it clear, Brian. What I want to implement is

Addr(15 downto C_controlBits) <= SignalB;
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;

I can't use the generated stuff here.

Thank you,
Rebecca
 
Jim:

I want to implement this
Addr(15 downto C_controlBits) <= SignalB;
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;

Sorry that I didn't describe it clear and you had to guess. You
suggestion is what I needed.
But is that a good idear to overwite it? I know it is handy, but would
it cause problem for syncrounous design because it induces extra
delay/
unstable phases and then probably data hazard?

Thank you very much,
Rebecca
 
If this has to be sequential code (inside a process), then Jim's
solution works fine:

Addr <= (others => '0');
Addr(15 downto C_controlBits) <= SignalB;

If this is supposed to be concurrent statements, then generate will
work, since C_control_bits must be static because signalB is of static
width.

Addr(15 downto C_controlBits) <= SignalB;
if C_controlBits /= 0 generate
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end generate;

Take your pick.

andy

On Mar 26, 10:36 am, "Rebecca" <pang.dudu.p...@hotmail.com> wrote:
Sorry I didn't describe it clear, Brian. What I want to implement is

Addr(15 downto C_controlBits) <= SignalB;
if(C_ControlBits=0) then
NULL;
else
Addr(C_ControlBits-1 downto 0) <= (others=>'0');
end if;

I can't use the generated stuff here.

Thank you,
Rebecca
Click to expand...
 
Thank you so much, Andy. I need both in my design.
Thanks a lot,
Rebecca
 
Thank you so much, Andy. I need both in my design.
Thanks a lot,
Rebecca
 
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