Question about clock edges

M

Mike

Guest
Hi,

I'm having trouble understanding how to use the clock edges and I'm hoping
someone can help me. To explain my problem a little better, take for
example the i2c protocol. The i2c protocol uses a clock (SCL) and data
(SDA) line. SDA is valid and must remain stable while SCL is high. SDA can
only change while SCL is low.

I understand that in my VHDL design I simply read SDA on the rising edge of
SCL, but when do I write (output) data to SDA? If I use the rising edge of
SCL to write to SDA, then won't other devices on the bus miss my data? I'm
thinking this because I assume other devices are also reading on the rising
edge of SCL. So how can I be sure that I can write the data before they
read it (if we both use the same clock edge)?

Using the falling edge as well as the rising edge seems an uncommon
practice. So I was wandering how else I can go about it. I'm not using
i2c, but it explains my problem quite well.

Thanks for any help with this,
 
On Wed, 6 Oct 2004 23:52:10 +0100, "Mike" <mike@mike.com> wrote:

Hi,

I'm having trouble understanding how to use the clock edges and I'm hoping
someone can help me. To explain my problem a little better, take for
example the i2c protocol. The i2c protocol uses a clock (SCL) and data
(SDA) line. SDA is valid and must remain stable while SCL is high. SDA can
only change while SCL is low.

I understand that in my VHDL design I simply read SDA on the rising edge of
SCL, but when do I write (output) data to SDA? If I use the rising edge of
SCL to write to SDA, then won't other devices on the bus miss my data? I'm
thinking this because I assume other devices are also reading on the rising
edge of SCL. So how can I be sure that I can write the data before they
read it (if we both use the same clock edge)?

Using the falling edge as well as the rising edge seems an uncommon
practice.
Click to expand...
It's commonly done in low speed interfaces. Using both edges of the
clock is a cheap, simple and effective way of dealing with skew.

It does, however, halve the available timing margin, which is why it's
never used for high speed interfaces.

Regards,
Allan
 
Hi

As other guys already mentioned negative and positive clock.
Their is one more option but not very common or realistic in nature.
You can use one more clock which is faster than this one.
Basically you have faster clock and you are using frequency divider for
generating slower clock.
 
Hi

As other guys already mentioned negative and positive clock.
Their is one more option but not very common or realistic in nature.
You can use one more clock which is faster than this one.
Basically you have faster clock and you are using frequency divider for
generating slower clock.
 
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message > It's commonly done in low speed interfaces. Using both edges of the
clock is a cheap, simple and effective way of dealing with skew.

It does, however, halve the available timing margin, which is why it's
never used for high speed interfaces.
Click to expand...
I'm not sure I agree with it not being able to be used for high speed
interfaces. If it's a good clock and if the FPGA supports it, one can
always use the (clk'falling_edge) expression. I'm not sure why you say
it would halve the timing margin.

Thanks,

- Paulo Valentim
 
On 7 Oct 2004 06:01:52 -0700, prv3299@yahoo.com (Paulo Valentim)
wrote:

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message > It's commonly done in low speed interfaces. Using both edges of the
clock is a cheap, simple and effective way of dealing with skew.

It does, however, halve the available timing margin, which is why it's
never used for high speed interfaces.


I'm not sure I agree with it not being able to be used for high speed
interfaces. If it's a good clock and if the FPGA supports it, one can
always use the (clk'falling_edge) expression. I'm not sure why you say
it would halve the timing margin.
Click to expand...
We were talking about clocking a signal *out* on one edge and sampling
it *in* on the other (e.g. rising to falling).
Clock to out delay + propagation delay + settling time + setup time +
skew < 1/2 a clock period in this case (depending on clock duty
cycle).

If the same edge was used, there would twice as much time (i.e. a full
clock period) available.


If you have plenty of timing margin when passing data between
different clock edges, it's not high speed!

Regards,
Allan
 
"Mike" <mike@mike.com> wrote in message news:<ck1sfg$9r6$1@newsg4.svr.pol.co.uk>...
Hi,

I'm having trouble understanding how to use the clock edges and I'm hoping
someone can help me. To explain my problem a little better, take for
example the i2c protocol. The i2c protocol uses a clock (SCL) and data
(SDA) line. SDA is valid and must remain stable while SCL is high. SDA can
only change while SCL is low.

I understand that in my VHDL design I simply read SDA on the rising edge of
SCL, but when do I write (output) data to SDA? If I use the rising edge of
SCL to write to SDA, then won't other devices on the bus miss my data? I'm
thinking this because I assume other devices are also reading on the rising
edge of SCL. So how can I be sure that I can write the data before they
read it (if we both use the same clock edge)?

Using the falling edge as well as the rising edge seems an uncommon
practice. So I was wandering how else I can go about it. I'm not using
i2c, but it explains my problem quite well.

Thanks for any help with this,
Click to expand...
Hi,
I have implemented this.I have used rising edge of clock to read
data and falling edge to drive the data onto SDA line.This can be
implemented with ease.I have a state machine which is invoked on the
rising edge.Control signals generated by the state machine are
observed during transmission on the falling edge.This is the reason i
feel I2C operate below 10 Mhz.

regards,
Raghavendra.Sortur
 
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