question about case

[billt]

I've not been able to find commentary on something I'd like to do with
a case statement, nothing says I can do this and nothing says I cannot
do this. I'd like to have multiple cases that have the same code, but I
don't want to type that code in more than once. In C, you can just
stick the cases together and the code for that group of cases comes
after the last one. Here's an example mimicking that in verilog:

case (system_state)
`STATE_READ_ARRAY :
`STATE_READ_ARRAY_LOW_FREQ :
begin
//do same thing for both of these read array states
end
`STATE_WRITE_ARRAY :
begin
//do something else
end
default :
begin
//somehow in unknown state, go back to idle or
something
end
endcase

For the first two cases, is it legal to do this? Or will the simulator
or synthesis tool have a problem with that, and I must duplicate the
code as:

case (system_state)
`STATE_READ_ARRAY :
begin
//do same thing for both of these read array states
end
`STATE_READ_ARRAY_LOW_FREQ :
begin
//do same thing for both of these read array states
end
`STATE_WRITE_ARRAY :
begin
//do something else
end
default :
begin
//somehow in unknown state, go back to idle or
something
end
endcase

Or if things must be "duplicated", should the code be made a task which
is called by both cases?

Thanks...

 

[Andy Ray]

This'll do what you intend.

Cheers,

Andy


case (system_state)
`STATE_READ_ARRAY, `STATE_READ_ARRAY_LOW_FREQ :
begin
//do same thing for both of these read array states
end
`STATE_WRITE_ARRAY :
begin
//do something else
end
default :
begin
end
endcase

 

billt wrote:

I've not been able to find commentary on something I'd like to do with
a case statement, nothing says I can do this and nothing says I cannot
do this. I'd like to have multiple cases that have the same code, but I
don't want to type that code in more than once. In C, you can just
stick the cases together and the code for that group of cases comes
after the last one. Here's an example mimicking that in verilog:

case (system_state)
`STATE_READ_ARRAY :
`STATE_READ_ARRAY_LOW_FREQ :
begin
//do same thing for both of these read array states
end

This syntax only works in C because each case falls through to the next
instead of branching to the end when it is done. To get this sharing
between cases in Verilog, you explicitly specify that there are
multiple values for this case item. You use a list of case expressions
separated by commas, followed by the colon, to say that everything in
this list goes to this item.