question about birdirectional bus.

[WGNoise@gmail.com]

hi,all
Here is some verilog code modeling bidirectional bus from example
6.22 Advanced Digital Design with the Verilog HDL authored by Michael
D. Ciletti.

module Bi_dir_bus(data_to_from_bus,send_data,rcv_data);
inout [31:0] data_to_from_bus;
input send_data,rcv_data;
wire [31:0] ckt_to_bus;
wire [31:0] data_to_from_bus,data_from_bus;

assign data_from_bus=(rcv_data)?data_to_from_bus:32'bz;

//*********************************confused about following
statement***//
assign data_to_from_bus=(send_data)?ckt_to_bus:data_to_from_bus;
//(*)
//**********************************//

//ckt_to_bus is reg_to bus in the book, which doesn't exsit in
declaration, so I change it to ckt_to_bus.

//some codes


endmodule

why instead of 32'bz data_to_from_bus exist in LHS? and doesn't this
synthesize to a latch?

 

[WGNoise@gmail.com]

errata and revision of this book had fixed this.

 

[dannoritzer@web.de]

Hi,

WGNoise@gmail.com schrieb:

hi,all
Here is some verilog code modeling bidirectional bus from example
6.22 Advanced Digital Design with the Verilog HDL authored by Michael
D. Ciletti.

....

I was searching for some information about this book. Amazon lists two
items with different ISBN numbers for this book:

http://www.amazon.com/exec/obidos/tg/detail/-/0130891614/qid=1121349304/sr=8-1/ref=pd_bbs_ur_1/104-0051547-7297548?v=glance&s=books&n=507846

and

http://www.amazon.com/exec/obidos/tg/detail/-/0131678442/qid=1121349304/sr=8-2/ref=sr_8_xs_ap_i1_xgl14/104-0051547-7297548?v=glance&s=books&n=507846

The two ISBN # are:

0130891614

and

0131678442

For the second ISBN # it says that it was published in December 2004.
Now does any one know whether that is a new version of the book or did
it just got re-packaged with a new software?

Googling for the second ISBN # I found the description ISE 6.3 student
edition.

Thanks for the help.

Guenter