Guest
Hi,
I learn Verilog on a web tutorial. There is only one line (item 4 below) which
makes me puzzled. Its comment after '//' is a general statement, not
specifically associated with 'a=~b'?
1. a = b + c ; // That was very easy
2. a = 1 << 5; // Hum let me think, ok shift '1' left by 5 positions.
3. a = !b ; // Well does it invert b???
4. a = ~b ; // How many times do you want to assign to 'a', it could cause
multiple-drivers.
I would get your experts explain it to me a little.
Thanks,
I learn Verilog on a web tutorial. There is only one line (item 4 below) which
makes me puzzled. Its comment after '//' is a general statement, not
specifically associated with 'a=~b'?
1. a = b + c ; // That was very easy
2. a = 1 << 5; // Hum let me think, ok shift '1' left by 5 positions.
3. a = !b ; // Well does it invert b???
4. a = ~b ; // How many times do you want to assign to 'a', it could cause
multiple-drivers.
I would get your experts explain it to me a little.
Thanks,