Question about 2 bit counter example.

S

Skybuck Flying

Guest
Hi,

I am new to electronics and VHDL etc.

I am trying to understand the first 2 bit counter example. In this PDF:

http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

I think the clock signal goes as follows:
high, low, high, low, high, low.

So that's just the same as:
101010101010101010101

The clock signal is connected to a T_flipflop and goes out port Q0 (and also
ff0 I dont understand what that is... just some internal state thing ? but
ok)

So after the clock signal passess through the T_flipflop the new signal will
look like:
old clock signal:
1010101010101010101010

( t_flipflop is explained at
http://en.wikipedia.org/wiki/Flip_flop#T_flip-flop )

new Q0 signal:
1100110011001100110011

Now the new Q0 signal also goes to another invertor...

So after the invertor the interver signal will look like:

( I think an invertor just inverts it right ? ;) )

Q0 inverter signal:
0011001100110011001100

Now the Q0 inverter signal enters another t_flipflop and it's output is Q1.
(also ff1)

Q1 signal:
001000100010001000100


So now we have three signals:

The original clock signal:
101010101010101010101010

The Q0 flipflop signal:
110011001100110011001100

The Q1 flipflop signal:
001000100010001000100010

Ok I find this a little bit weird.

For a counter I would expect the output to be the following:
Q0 Q1:

00
01
10
11
00
01
10
11

However the output seems to be:

10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00

This is totally different than how I would expect it too work...

Have I made a mistake in my reasoning somewhere ?

Is there a part I dont understand ? maybe the invertor works differently ?

Or is the PDF/manual a weird/bogus/wrong example of a 2 bit counter ???

Bye,
Skybuck.
 
"Skybuck Flying" <nospam@hotmail.com> wrote in message news:...
Hi,

I am new to electronics and VHDL etc.

I am trying to understand the first 2 bit counter example. In this PDF:


http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

I think the clock signal goes as follows:
high, low, high, low, high, low.

So that's just the same as:
101010101010101010101

The clock signal is connected to a T_flipflop and goes out port Q0 (and
also
ff0 I dont understand what that is... just some internal state thing ? but
ok)

So after the clock signal passess through the T_flipflop the new signal
will
look like:
old clock signal:
1010101010101010101010

( t_flipflop is explained at
http://en.wikipedia.org/wiki/Flip_flop#T_flip-flop )

new Q0 signal:
1100110011001100110011

Now the new Q0 signal also goes to another invertor...

So after the invertor the interver signal will look like:

( I think an invertor just inverts it right ? ;) )

Q0 inverter signal:
0011001100110011001100

Now the Q0 inverter signal enters another t_flipflop and it's output is
Q1.
(also ff1)

Q1 signal:
001000100010001000100


So now we have three signals:

The original clock signal:
101010101010101010101010

The Q0 flipflop signal:
110011001100110011001100

The Q1 flipflop signal:
001000100010001000100010

Ok I find this a little bit weird.

For a counter I would expect the output to be the following:
Q0 Q1:

00
01
10
11
00
01
10
11

However the output seems to be:

10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00
10
10
01
00

This is totally different than how I would expect it too work...

Have I made a mistake in my reasoning somewhere ?

Is there a part I dont understand ? maybe the invertor works differently ?

Or is the PDF/manual a weird/bogus/wrong example of a 2 bit counter ???
Click to expand...
The problem is I don't understand picture/figure 1-2.

If I work out how the bits move through it I don't see the desired result...
?

Can anybody explain figure 1-2 ???

Bye,
Skybuck.
 
Ok,

Now I understand how these electronics work...

But I do find it very weird indeed ;)

First of all the t flip flop only changes state on a fall from 1 to 0 (some
flip flops might work opposite but ok)

Second of all, apperently the "outputs" of the construction/entity has to be
read at the same rate as the clock rate.

Otherwise it doesn't make much sense.

The first mistake I made was assuming that every 1 bit during the clock rate
would convert the flip flop.

But this is not the case... the flip flop only changes when the 1 change
from 1 to zero or vice versa...

So my first assumption that it worked like this was wrong:

11001100110011001100

Suppose a flip flop was connected to this bit stream.

I thought that each 1 would convert the next flip flop like this:
10001000100010001000

Which is wrong ;)

The flip flop only changes when the input changes from 1 to zero.

So given the input stream:
11001100110011001100

The flip flop output stream would be:
( assuming it changes on a fall from 1 to zero)
00111100001111000011

Etc... truely halving the signal etc.

Now the last tricky part is in reading the outputs...

Let's draw it one more time:

Clock rate: 01010101010101010101
Q1 : 00110011001100110011
Inverter : 11001100110011001100
Q2 : 00001111000011110000

So filtering out Q1 and Q2:

Q1 : 00110011001100110011
Q2 : 00001111000011110000

At first glance this doesn't seem to make any sense at all ;)

The output would be:
00
00
10
10
01
01
11
11
00

The output should look like:
00
01
10
11
00
01
etc

So the funny thing with electronics is that the signal has to be stable for
a while.

So the signal has to be read... and apperently this happens at the same rate
as the clock rate ? ;)

So we need to use the clock rate to figure it out ;)
01 = one clock tick


Clock rate: 01#01#01#01#01#01#01#01#01#01
Q1 : 00#11#00#11#00#11#00#11#00#11
Q2 : 00#00#11#11#00#00#11#11#00#00

Reading Q1 and Q2 during the clock tick gives the following stable result:

Q1 : 0#1#0#1#0#1#0#1#0#1
Q2 : 0#0#1#1#0#0#1#1#0#0

Now putting this next to each other:

Q1, Q2
00
10
01
11
00
10
01
11

This looks a bit better ;)

Maybe we need to switch em around ;)

Q2, Q1
00
01
10
11
00
01
10
11

Ah, now we have our desired result :)

Electronics are damn tricky ! :)

Bye,
Skybuck =D
 
"Skybuck Flying" <nospam@hotmail.com> wrote in message news:...
Ok,

Now I understand how these electronics work...

But I do find it very weird indeed ;)

First of all the t flip flop only changes state on a fall from 1 to 0
(some
flip flops might work opposite but ok)

Second of all, apperently the "outputs" of the construction/entity has to
be
read at the same rate as the clock rate.

Otherwise it doesn't make much sense.

The first mistake I made was assuming that every 1 bit during the clock
rate
would convert the flip flop.

But this is not the case... the flip flop only changes when the 1 change
from 1 to zero or vice versa...

So my first assumption that it worked like this was wrong:

11001100110011001100

Suppose a flip flop was connected to this bit stream.

I thought that each 1 would convert the next flip flop like this:
10001000100010001000

Which is wrong ;)

The flip flop only changes when the input changes from 1 to zero.

So given the input stream:
11001100110011001100

The flip flop output stream would be:
( assuming it changes on a fall from 1 to zero)
00111100001111000011

Etc... truely halving the signal etc.

Now the last tricky part is in reading the outputs...

Let's draw it one more time:

Clock rate: 01010101010101010101
Q1 : 00110011001100110011
Inverter : 11001100110011001100
Q2 : 00001111000011110000
Click to expand...
Oops I see I messed up here :)

Had to take the inverter for Q2 ;)

Clock rate: 01010101010101010101
Q1 : 00110011001100110011
Inverter : 11001100110011001100
Q2 : 00111100001111000011

So filtering out Q1 and Q2:

Q1 : 00110011001100110011
Q2 : 00111100001111000011

Clock rate: 01#01#01#01#01#01#01#01#01#01
Q1 : 00#11#00#11#00#11#00#11#00#11
Q2 : 00#11#11#00#00#11#11#00#00#11

Reading Q1 and Q2 during the clock tick gives the following stable result:

Q1 : 0#1#0#1#0#1#0#1#0#1
Q2 : 0#1#1#0#0#1#1#0#0#1

Now putting this next to each other:

Q1, Q2
00
11
01
10
00
11
01
10
00
11
01

Yeah maybe we still need to switch em around ;)

Q2, Q1

00
11
10
01
00
11
10
01
00
11
10

Ok this looks a bit better ;)

Apprently a countdown counter ?

Or did I mess up again somewhere ? ;)

Tricky, tricky,tricky,tricky :)

Bye,
Skybuck.
 
Hmm the code below figure 1-2 of the vhdl cookbook seems to be an
incrementing counter.

count:=(count + 1) mod 4
Q1 := count_value mod 2
Q2 := count_value / 2

count value: 0,1,2,3,0,1,2,3
Q1 : 0,1,0,1,0,1,0,1
Q2 : 0,0,1,1,0,0,1,1

While my output shows a decrementing counter.

Could it be that the cookbook has a wrong picture ?

Or is there still a flaw somewhere in my reasoning ? ;)

http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Bye,
Skybuck

"Skybuck Flying" <nospam@hotmail.com> wrote in message news:...
"Skybuck Flying" <nospam@hotmail.com> wrote in message news:...
Ok,

Now I understand how these electronics work...

But I do find it very weird indeed ;)

First of all the t flip flop only changes state on a fall from 1 to 0
(some
flip flops might work opposite but ok)

Second of all, apperently the "outputs" of the construction/entity has
to
be
read at the same rate as the clock rate.

Otherwise it doesn't make much sense.

The first mistake I made was assuming that every 1 bit during the clock
rate
would convert the flip flop.

But this is not the case... the flip flop only changes when the 1 change
from 1 to zero or vice versa...

So my first assumption that it worked like this was wrong:

11001100110011001100

Suppose a flip flop was connected to this bit stream.

I thought that each 1 would convert the next flip flop like this:
10001000100010001000

Which is wrong ;)

The flip flop only changes when the input changes from 1 to zero.

So given the input stream:
11001100110011001100

The flip flop output stream would be:
( assuming it changes on a fall from 1 to zero)
00111100001111000011

Etc... truely halving the signal etc.

Now the last tricky part is in reading the outputs...

Let's draw it one more time:

Clock rate: 01010101010101010101
Q1 : 00110011001100110011
Inverter : 11001100110011001100
Q2 : 00001111000011110000

Oops I see I messed up here :)

Had to take the inverter for Q2 ;)

Clock rate: 01010101010101010101
Q1 : 00110011001100110011
Inverter : 11001100110011001100
Q2 : 00111100001111000011

So filtering out Q1 and Q2:

Q1 : 00110011001100110011
Q2 : 00111100001111000011

Clock rate: 01#01#01#01#01#01#01#01#01#01
Q1 : 00#11#00#11#00#11#00#11#00#11
Q2 : 00#11#11#00#00#11#11#00#00#11

Reading Q1 and Q2 during the clock tick gives the following stable result:

Q1 : 0#1#0#1#0#1#0#1#0#1
Q2 : 0#1#1#0#0#1#1#0#0#1

Now putting this next to each other:

Q1, Q2
00
11
01
10
00
11
01
10
00
11
01

Yeah maybe we still need to switch em around ;)

Q2, Q1

00
11
10
01
00
11
10
01
00
11
10

Ok this looks a bit better ;)

Apprently a countdown counter ?

Or did I mess up again somewhere ? ;)

Tricky, tricky,tricky,tricky :)

Bye,
Skybuck.
Click to expand...
 
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