Questasim Equivalent commands for Icarus Verilog

[RSGUPTA]

Hi Folks,
There are commands in Icarus tool for compiling verilog files as given
below:
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file

and then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.

If the same operation is to be done in Questasim what are the
equivalent commands??

Thanks in advance.

 

[Jonathan Bromley]

On Tue, 2 Sep 2008 03:31:46 -0700 (PDT), RSGUPTA wrote:

There are commands in Icarus tool for compiling verilog
files as given below:
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file

I guess "files.txt" contains a list of the Verilog files
you want to compile? That's known as a "response file"
or "gather file". In most commercial Verilog compilers
you can use such a file with the -f compiler switch:

vlog -f files.txt # for Mentor simulators

But first you must have created a working library,
or else the vlog command will complain. So the correct
sequence is:

vlib work # do this the first time, once only
vlog -f files.txt # compile all the files

and then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.

Now you need to know the name of the top-level module(s) in
your simulation, so you can do...

vsim top_module_name

If the same operation is to be done in Questasim what are the
equivalent commands??

You may find it easier to use the one-shot command

qverilog -gui -f files.txt

which automatically builds a library, compiles everything
in your file list, works out which are the top-level modules
and simulates them. Similar commands exist for other
mainstream simulators; these happen to spring to mind:

irun -gui -f files.txt # Cadence Incisive
vcs -R -f files.txt # Synopsys VCS

And guess what, it's usually all in the documentation.
Though I agree that it's often easier to ask someone
who's done it before, just to get started.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[RSGUPTA]

On Sep 3, 1:59 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Tue, 2 Sep 2008 03:31:46 -0700 (PDT), RSGUPTA wrote:
There are commands in Icarus tool for compiling verilog
files as given below:
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file

I guess "files.txt" contains a list of the Verilog files
you want to compile?  That's known as a "response file"
or "gather file".  In most commercial Verilog compilers
you can use such a file with the -f compiler switch:

  vlog -f files.txt  # for Mentor simulators

But first you must have created a working library,
or else the vlog command will complain. So the correct
sequence is:

 vlib work         # do this the first time, once only
 vlog -f files.txt # compile all the files

and then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.

Now you need to know the name of the top-level module(s) in
your simulation, so you can do...

  vsim top_module_name

If the same operation is to be done in Questasim what are the
equivalent commands??

You may find it easier to use the one-shot command

  qverilog -gui -f files.txt

which automatically builds a library, compiles everything
in your file list, works out which are the top-level modules
and simulates them.  Similar commands exist for other
mainstream simulators; these happen to spring to mind:

  irun -gui -f files.txt    # Cadence Incisive
  vcs -R -f files.txt       # Synopsys VCS

And guess what, it's usually all in the documentation.
Though I agree that it's often easier to ask someone
who's done it before, just to get started.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan Bromley,
Thanks for Your Reply.
Well I did follow up your steps to compile and simulate, but found
some issues ...These were all the commands I used up to get my
simulation running.
vlib work
vlog -f rtl/files.txt
vsim -c top_module_name -do "log -r /*; run -all"
wlf2vcd vsim.wlf > dump.vcd
gtkwave dump.vcd &

Message: No signals found matching /* and no gtkwave window opened up.

Where as when i ran the simulation using icarus i had no issues in
viewing the waveforms as all the signals were visible in it with these
3 commands.
iverilog -c rtl/files.txt
vvp a.out
gtkwave dump.vcd &

I beleive there is some flow difference in the 2 simulators in
generating the intermediate files and then finally viewing the
waveforms from the dump files like the formation of a.out file which
is not generated by Questasim.

 

[Kim Enkovaara]

RSGUPTA wrote:

...
vsim -c top_module_name -do "log -r /*; run -all"
wlf2vcd vsim.wlf > dump.vcd
gtkwave dump.vcd &

Message: No signals found matching /* and no gtkwave window opened up.
...
I beleive there is some flow difference in the 2 simulators in
generating the intermediate files and then finally viewing the
waveforms from the dump files like the formation of a.out file which
is not generated by Questasim.

You can also use Modelsim waveform viewer that is much better than the
gtkwave. The internal viewer can be used during simulation etc. So you
can check that everything is going ok during the simulation etc.

But there is also another way of creating vcd files, from the prompt
you can say

VSIM> vcd file foobar.vcd
VSIM> vcd add /*
VSIM> run -all
VSIM> quit -f

The ideology behind modelsim is little different compared to ncverilog
and vcs (and icarus). My own preference is the modelsim way of doing
things, altough the new vopt flow is a step backwards. I suggest you
read the manual, there are good examples about the different verilog
flows (and how the optimization works).

--Kim

 

[NigelE]

Hi Jonathan Bromley,
Thanks for Your Reply.
Well I did follow up your steps to compile and simulate, but found
some issues ...These were all the commands I used up to get my
simulation running.
vlib work
vlog -f rtl/files.txt
vsim -c top_module_name -do "log -r /*; run -all"
wlf2vcd vsim.wlf > dump.vcd
gtkwave  dump.vcd &

Message: No signals found matching /* and no gtkwave window opened up.

Jonathan's compile suggestions did not cover the steps required to
enable debug in Questa.

By default, Questa will compile a design for maximun performance.
This means that access to internal signals is disabled, as it slows
the simulator.

The global optimization of a design is done using the vopt command.
This can be called explicitly (between the vlog and vsim steps) or
implicitly as part of the vsim command.

With your script, enable full debug with the following:

vlib work
vlog -f rtl/files.txt
vsim -c top_module_name -voptargs="+acc" -do "log -r /*; run -all"

Hope this helps

cheers

- Nigel
Mentor Graphics