questa file IO

[Verictor]

Hi,

I don't know what I am missing in the following simple file: I have
correct print out of the text file but there is no display in the
waveform window. More specific, data_in and dummy display correctly in
the shell window but all show 0's in the waveform window.

This is Questasim 6.5. The input data file is simple a text file.

module vtest();

reg clk;
reg rst;
reg data_in;

reg dummy;

integer fileID;

parameter CLK_PERIOD = 10.0;

initial begin
clk = 1'b0;
forever begin
#(CLK_PERIOD/2) clk = !clk;
end
end

initial begin
rst = 1'b1;
repeat(10) @(posedge clk);
rst = 1'b0;
end

initial begin
fileID = $fopen("u_input.txt", "r");
dummy = 1'b0;
end

always @(negedge clk) begin
while (!$feof(fileID)) begin
if ($fscanf(fileID, "%x", data_in)) begin
$display("data %d", data_in);
dummy = data_in;
$display("dummy %x", dummy);
end
end
end


endmodule

 

[Muzaffer Kal]

On Wed, 1 Dec 2010 19:08:35 -0800 (PST), Verictor <stehuang@gmail.com>
wrote:

Hi,

I don't know what I am missing in the following simple file: I have
correct print out of the text file but there is no display in the
waveform window. More specific, data_in and dummy display correctly in
the shell window but all show 0's in the waveform window.

....
always @(negedge clk) begin
while (!$feof(fileID)) begin
if ($fscanf(fileID, "%x", data_in)) begin
$display("data %d", data_in);
dummy = data_in;
$display("dummy %x", dummy);
end
end
end

Your problem is that the always @(negedge clk) is outside the while
loop. If you want one read per clk, you need to reverse the order.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com