Quartus ripple clock

Hi everybody,

I made a clock "clock_baud" with the output of a counter and Quartus
give me this message :

"Warning : Found 1 node in clock path which may be acting as ripple
and/or gated clocks -- node analyzed as buffer resulting in clock skew"
"Info : Detected ripple clock clock_baud~reg0 as buffer"

This is my process which generate the clock_baud.
then in another process I use clock_baud as a clock with
rising_edge(clock_baud)

Do you know how to write the VHDL ?

Thanks

GEN_CLK_BAUD_1 : process (clk_smp,reset)
variable compteur : natural range 0 to N_max*Over_X + 1;
variable ck_baud : std_logic;

begin
if reset='1' then
clock_baud <= '1';
ck_baud := '1';
elsif (clk_smp'event and clk_smp='1') then
if (start_raz ='1' or preum_start='0' or compteur N*Over_X-1) then
compteur := 0;
else
compteur := compteur + 1;
end if;

-- Génčre l'horloge symbole
if compteur <= N*2 then
ck_baud := '1';
else
ck_baud := '0';
end if;
clock_baud <= ck_baud;

end if;
end process GEN_CLK_BAUD_1;
end fonc;

 

[Noway2]

Quartus will give you a warning any time it detects that you are using
a signal as a clock that hasn't been declared as such. This is
especially true if you are using a clock that is derived by logic, even
off of a flip-flop output as in a clock divider. The problem is that
without more information on the timing requirements, that the timingi
analyzer can't determine if there are any violations.

The problem is fairly easy to rectify. What you can do, is select the
block reference, in this case, clock_buad-reg0, and define this is a
derived clock in the timing settings. I say derived clock, assuming
that the clock rate is derived from a known signal. If it is not, you
can specify it as an independant clock and provide the clock
specifications.

Once quartus is armed with this information, it should be able to
determine if there is a timing problem with the fit and hopefully there
will no longer be a warning message. I have often times found that
when I attempt to implement a build with this warning that the
circuitry does not work as intended.

 

Effectively, I tried the design with the warning and that not work
correctly.
So I declared the clock as a derived clock and with the correct offset
and that compile very well.

Thanks.