B
Blackie Beard
Guest
Hi;
I have a rom file for custom processor. I don't want to
use Quatus ROM Megafunctions because it's compiler
doesn't like intel hex files other that for byte-wide data,
and my data is 12 bits wide. So I wrote a custom utility
to create a ROM file (see at bottom of this post).
I know this may just be a Quartus quirk, but I want to
make sure it's not my verilog before I harass their techs.
My question is two-fold
1. Why does Quartus synthesize so that 800h word
ROM block uses A00h words? That is, I calculate that
worse case I should use 24,576 mem bits, yet Quartus
takes 30,720. If I prepend an "if(addr == 11'h7FF..."
and pull that out of the case statement, then it does
synthesize to the correct amount of memory. Why?
2. Is there simple way I'm overlooking to improve the
syntax or format or something to make the compiler
actually use only the memory bits that I actually use
(short of "if the address is within some range" stuff)?
Now here's the file in case anyone wants to test it:
module rom (
addr,
data
);
input [10:0] addr;
output [11:0] data;
reg [11:0] data;
always @(addr)
case (addr)
11'h000 : data = 12'h061;
11'h001 : data = 12'h004;
11'h002 : data = 12'hC07;
11'h003 : data = 12'h002;
11'h004 : data = 12'hC01;
11'h005 : data = 12'h021;
11'h006 : data = 12'hC17;
11'h007 : data = 12'h028;
11'h008 : data = 12'h201;
11'h009 : data = 12'h743;
11'h00a : data = 12'hA08;
11'h00b : data = 12'hC01;
11'h00c : data = 12'h021;
11'h00d : data = 12'h0E8;
11'h00e : data = 12'h743;
11'h00f : data = 12'hA08;
11'h010 : data = 12'h800;
11'h011 : data = 12'h064;
11'h012 : data = 12'hCFE;
11'h013 : data = 12'h006;
11'h014 : data = 12'hC30;
11'h015 : data = 12'h024;
11'h016 : data = 12'h580;
11'h017 : data = 12'h480;
11'h018 : data = 12'h720;
11'h019 : data = 12'hA18;
11'h01a : data = 12'h900;
11'h01b : data = 12'h5E0;
11'h01c : data = 12'h5A0;
11'h01d : data = 12'h4A0;
11'h01e : data = 12'h740;
11'h01f : data = 12'hA1E;
11'h020 : data = 12'h000;
11'h021 : data = 12'h000;
11'h022 : data = 12'h5C0;
11'h023 : data = 12'h600;
11'h024 : data = 12'hA23;
11'h025 : data = 12'h506;
11'h026 : data = 12'hA26;
11'h7FF : data = 12'h45C;
default : data = 12'h000;
endcase
endmodule
Thanks much!
BB
I have a rom file for custom processor. I don't want to
use Quatus ROM Megafunctions because it's compiler
doesn't like intel hex files other that for byte-wide data,
and my data is 12 bits wide. So I wrote a custom utility
to create a ROM file (see at bottom of this post).
I know this may just be a Quartus quirk, but I want to
make sure it's not my verilog before I harass their techs.
My question is two-fold
1. Why does Quartus synthesize so that 800h word
ROM block uses A00h words? That is, I calculate that
worse case I should use 24,576 mem bits, yet Quartus
takes 30,720. If I prepend an "if(addr == 11'h7FF..."
and pull that out of the case statement, then it does
synthesize to the correct amount of memory. Why?
2. Is there simple way I'm overlooking to improve the
syntax or format or something to make the compiler
actually use only the memory bits that I actually use
(short of "if the address is within some range" stuff)?
Now here's the file in case anyone wants to test it:
module rom (
addr,
data
);
input [10:0] addr;
output [11:0] data;
reg [11:0] data;
always @(addr)
case (addr)
11'h000 : data = 12'h061;
11'h001 : data = 12'h004;
11'h002 : data = 12'hC07;
11'h003 : data = 12'h002;
11'h004 : data = 12'hC01;
11'h005 : data = 12'h021;
11'h006 : data = 12'hC17;
11'h007 : data = 12'h028;
11'h008 : data = 12'h201;
11'h009 : data = 12'h743;
11'h00a : data = 12'hA08;
11'h00b : data = 12'hC01;
11'h00c : data = 12'h021;
11'h00d : data = 12'h0E8;
11'h00e : data = 12'h743;
11'h00f : data = 12'hA08;
11'h010 : data = 12'h800;
11'h011 : data = 12'h064;
11'h012 : data = 12'hCFE;
11'h013 : data = 12'h006;
11'h014 : data = 12'hC30;
11'h015 : data = 12'h024;
11'h016 : data = 12'h580;
11'h017 : data = 12'h480;
11'h018 : data = 12'h720;
11'h019 : data = 12'hA18;
11'h01a : data = 12'h900;
11'h01b : data = 12'h5E0;
11'h01c : data = 12'h5A0;
11'h01d : data = 12'h4A0;
11'h01e : data = 12'h740;
11'h01f : data = 12'hA1E;
11'h020 : data = 12'h000;
11'h021 : data = 12'h000;
11'h022 : data = 12'h5C0;
11'h023 : data = 12'h600;
11'h024 : data = 12'hA23;
11'h025 : data = 12'h506;
11'h026 : data = 12'hA26;
11'h7FF : data = 12'h45C;
default : data = 12'h000;
endcase
endmodule
Thanks much!
BB