Quartus II simulation question.

C

Christos

Guest
Hi all,

In the vector waveform file that I am creating to enter the inputs for my
simulation I can also enter the outputs and the registers that I would like
to be recorded.
There using the node finder I can enter some combinatorial signals that I
would like to observe.
But after the simulation those signals have been omitted and the warning has
been given :
"Warning: Ignored node in vector source file. Can't find corresponding node
name CFCstatus in design."

So, can someone please explain me how I can check those internal signals?
For example the output of a lpm_compare block which feeds an input of a
counter without inserting in the middle a output pin? (you don't have to use
this example of course).

I thing it doesn't make any difference the version but I am using Quartus II
3.0.

Thanks,
Christos
 
PCB Quartus 2003

Altera Quartus II 2.2

11 104

ALTERA QUARTUS II V3.0

12 814

for more info, please send e-mail
 
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bm3agi$gr9$1@sunnews.cern.ch>...
Hi all,

In the vector waveform file that I am creating to enter the inputs for my
simulation I can also enter the outputs and the registers that I would like
to be recorded.
There using the node finder I can enter some combinatorial signals that I
would like to observe.
But after the simulation those signals have been omitted and the warning has
been given :
"Warning: Ignored node in vector source file. Can't find corresponding node
name CFCstatus in design."

So, can someone please explain me how I can check those internal signals?
For example the output of a lpm_compare block which feeds an input of a
counter without inserting in the middle a output pin? (you don't have to use
this example of course).

I thing it doesn't make any difference the version but I am using Quartus II
3.0.

Thanks,
Christos
Click to expand...
Hi Christos,

To preserve a combinatorial node through synthesis, place and route,
you should do one of the following:

a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal
that you are interested in observing into a LCELL primitive, and give
the LCELL primitive an interesting name, so that you can find it when
you choose the Post Compilation filter in the node finder. You should
feed the output of the LCELL to where the signal wof interes was
previously connected.

b) If you are using VHDL or Verilog, consider using the keep
pragma/keyword. Its usage is described in the online help. Search for
"keep". The Verilog help panel is shown below:

------------------- keep usage in Verilog
-----------------------------------
A Verilog HDL language directive that directs Analysis & Synthesis to
keep a particular wire intact. You can use this language directive to
keep a combinational logic node so you can observe the node during
simulation or with the SignalTapŽ II Logic Analyzer.

You cannot use this language directive for nodes that have no fan-out.

To use the keep language directive, you can specify the keep language
directive in a comment that is on the same line as the register you
want Analysis & Synthesis to preserve. In the comment, precede the
language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis preserve
*/ directs Analysis & Synthesis to not minimize the keep_wire
register:

wire keep_wire /* synthesis keep */;

-------------------------------------------------------------------------------

You would search for keep_wire in the Mode Finder.

Hope this helps.

- Subroto Datta
Altera Corp.
 
Hi Subroto,

Thanks once again for your help, its working great.

Christos



"Subroto Datta" <sdatta@altera.com> wrote in message
news:ca4d800d.0310091159.10bc0751@posting.google.com...
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message
news:<bm3agi$gr9$1@sunnews.cern.ch>...
Hi all,

In the vector waveform file that I am creating to enter the inputs for
my
simulation I can also enter the outputs and the registers that I would
like
to be recorded.
There using the node finder I can enter some combinatorial signals that
I
would like to observe.
But after the simulation those signals have been omitted and the warning
has
been given :
"Warning: Ignored node in vector source file. Can't find corresponding
node
name CFCstatus in design."

So, can someone please explain me how I can check those internal
signals?
For example the output of a lpm_compare block which feeds an input of a
counter without inserting in the middle a output pin? (you don't have to
use
this example of course).

I thing it doesn't make any difference the version but I am using
Quartus II
3.0.

Thanks,
Christos

Hi Christos,

To preserve a combinatorial node through synthesis, place and route,
you should do one of the following:

a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal
that you are interested in observing into a LCELL primitive, and give
the LCELL primitive an interesting name, so that you can find it when
you choose the Post Compilation filter in the node finder. You should
feed the output of the LCELL to where the signal wof interes was
previously connected.

b) If you are using VHDL or Verilog, consider using the keep
pragma/keyword. Its usage is described in the online help. Search for
"keep". The Verilog help panel is shown below:

------------------- keep usage in Verilog
-----------------------------------
A Verilog HDL language directive that directs Analysis & Synthesis to
keep a particular wire intact. You can use this language directive to
keep a combinational logic node so you can observe the node during
simulation or with the SignalTapŽ II Logic Analyzer.

You cannot use this language directive for nodes that have no fan-out.

To use the keep language directive, you can specify the keep language
directive in a comment that is on the same line as the register you
want Analysis & Synthesis to preserve. In the comment, precede the
language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis preserve
*/ directs Analysis & Synthesis to not minimize the keep_wire
register:

wire keep_wire /* synthesis keep */;

--------------------------------------------------------------------------
-----

You would search for keep_wire in the Mode Finder.

Hope this helps.

- Subroto Datta
Altera Corp.
Click to expand...
 
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