Quartus-II question

[Pratip Mukherjee]

Hi,
I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA.
Timing summary tells me that maximum clock is 11.xxx MHz. Since my external
clock is 40MHz, I inserted a divide by 4 counter before feeding it to the
CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's
that, shouldn't it be now 44.xxx MHz, assuming the input counter can count
to 44MHz. I am not using the input clock for any other purpose than
dividing by 4.
Another related question. ACEX1K datasheet says that the -3 devices do not
have PLL. But Quartus always reports 0 of 1 PLL used, even when I
specifically select -3 device. Which one is right, datasheet or Quartus?
Thanks in advance.

Pratip Mukherjee

 

[Andy Peters]

Pratip Mukherjee <pratipm_nooospam@hotmail.com> wrote in message news:<Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77>...

Hi,
I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA.
Timing summary tells me that maximum clock is 11.xxx MHz. Since my external
clock is 40MHz, I inserted a divide by 4 counter before feeding it to the
CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's
that, shouldn't it be now 44.xxx MHz, assuming the input counter can count
to 44MHz. I am not using the input clock for any other purpose than
dividing by 4.
Another related question. ACEX1K datasheet says that the -3 devices do not
have PLL. But Quartus always reports 0 of 1 PLL used, even when I
specifically select -3 device. Which one is right, datasheet or Quartus?
Thanks in advance.

Consider asking this question in the proper forum: comp.arch.fpga.

-a

 

[George]

Pratip Mukherjee <pratipm_nooospam@hotmail.com> wrote in message news:<Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77>...

Hi,
I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA.
Timing summary tells me that maximum clock is 11.xxx MHz. Since my external
clock is 40MHz, I inserted a divide by 4 counter before feeding it to the
CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's
that, shouldn't it be now 44.xxx MHz, assuming the input counter can count
to 44MHz. I am not using the input clock for any other purpose than
dividing by 4.
Another related question. ACEX1K datasheet says that the -3 devices do not
have PLL. But Quartus always reports 0 of 1 PLL used, even when I
specifically select -3 device. Which one is right, datasheet or Quartus?
Thanks in advance.

Pratip Mukherjee

Purely a point of view issue. Quartus is stating that you better not
go faster than 11.xxx. If you put the divide by 4 external to the
FPGA I'm sure you would be ok. If you can guarantee you seperated the
clocks then I'm also sure your OK.

One way is to put the 44.xxx into one clock input and divide then that
the output and wire it external to the FPGA into the other clock
input.

George

 

[Subroto Datta]

The PLL report for the ACEX1K -3 is a bug. This device does not have a PLL,
and this is a reporting bug which has been fixed in the next version of
Quartus. Without seeing your design, the best I can say for the timing
problem, is that you need to tell Quartus of the relationship between your
10Mhz derived clock and the 40 MHz external clock. You can do this using the
Assignment Settings->Timing Requirements and Options Dialog. The steps are
as follows, based on the assumption that your incoming 40 Mhz clock is
clock40.

1. Open Assignment Settings->Timing Requirements and Options Dialog
2. In the Clock Settings Group select the Settings for Individual clock
signals.
3. Click on the New button to define the new clock.
4. Fill in the entries in the New clock settings dialog. Set the clock
settings name to clock40 (for ease of use) and the "Applies to node" should
be selected to be the pin from the Node finder. The "Relationship to other
clock settings" should be set to "independent of other clock settings". The
fmax should be 40Mhz. Hit OK to close the New clock settings dialog box.
5. Next define the 11 MHz clock based on the output of the divide by 4.
Click on the New button to define clock10.
6. Set the clock settings name to clock10. The Applies to node should be the
output of the register that is the 10MHz signal. The "Relationship to other
clock settings" should be set to "Based on" clock40 (defined in step4).
Click on the Derived Clock Requirements, and fill in the Divide base clock
field.Hit OK, and close all the dialogs.
7. Compile the design.

Hope this helps

- Subroto Datta
Altera Corp.

"Pratip Mukherjee" <pratipm_nooospam@hotmail.com> wrote in message
news:Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77...

Hi,
I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA.
Timing summary tells me that maximum clock is 11.xxx MHz. Since my
external
clock is 40MHz, I inserted a divide by 4 counter before feeding it to the
CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's
that, shouldn't it be now 44.xxx MHz, assuming the input counter can count
to 44MHz. I am not using the input clock for any other purpose than
dividing by 4.
Another related question. ACEX1K datasheet says that the -3 devices do not
have PLL. But Quartus always reports 0 of 1 PLL used, even when I
specifically select -3 device. Which one is right, datasheet or Quartus?
Thanks in advance.

Pratip Mukherjee

 

[Pratip Mukherjee]

Thank you very much. That solved my problem.

-- Pratip Mukherjee

"Subroto Datta" <sdatta@altera.com> wrote in
news:OoaBb.4440$bc1.866@newssvr33.news.prodigy.com:

The PLL report for the ACEX1K -3 is a bug. This device does not have a
PLL, and this is a reporting bug which has been fixed in the next
version of Quartus. Without seeing your design, the best I can say for
the timing problem, is that you need to tell Quartus of the
relationship between your 10Mhz derived clock and the 40 MHz external
clock. You can do this using the Assignment Settings->Timing
Requirements and Options Dialog. The steps are as follows, based on
the assumption that your incoming 40 Mhz clock is clock40.

1. Open Assignment Settings->Timing Requirements and Options Dialog
2. In the Clock Settings Group select the Settings for Individual
clock signals.
3. Click on the New button to define the new clock.
4. Fill in the entries in the New clock settings dialog. Set the clock
settings name to clock40 (for ease of use) and the "Applies to node"
should be selected to be the pin from the Node finder. The
"Relationship to other clock settings" should be set to "independent
of other clock settings". The fmax should be 40Mhz. Hit OK to close
the New clock settings dialog box. 5. Next define the 11 MHz clock
based on the output of the divide by 4. Click on the New button to
define clock10. 6. Set the clock settings name to clock10. The Applies
to node should be the output of the register that is the 10MHz signal.
The "Relationship to other clock settings" should be set to "Based on"
clock40 (defined in step4). Click on the Derived Clock Requirements,
and fill in the Divide base clock field.Hit OK, and close all the
dialogs. 7. Compile the design.

Hope this helps

- Subroto Datta
Altera Corp.

"Pratip Mukherjee" <pratipm_nooospam@hotmail.com> wrote in message
news:Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77...
Hi,
I am trying to use AVRCore project from opencores.com on ACEX1K100-3
FPGA. Timing summary tells me that maximum clock is 11.xxx MHz. Since
my
external
clock is 40MHz, I inserted a divide by 4 counter before feeding it to
the CPU clock. But Quartus still says that max. clock is 11.xxx MHz.
How's that, shouldn't it be now 44.xxx MHz, assuming the input
counter can count to 44MHz. I am not using the input clock for any
other purpose than dividing by 4.
Another related question. ACEX1K datasheet says that the -3 devices
do not have PLL. But Quartus always reports 0 of 1 PLL used, even
when I specifically select -3 device. Which one is right, datasheet
or Quartus? Thanks in advance.

Pratip Mukherjee