Quartus-II 7.2 web-edition Systemverilog improvements

[Systemv User]

Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor:

`define SET_REG( x, y ) reg_``y <= x
`define CONCAT( x, y, z ) x``_``y``_``z

assign `CONCAT( bus0, func1, endpoint0 ) = 1'b0;

and named 'end' blocks:

module x;
...
always_comb begin : my_junk

end : my_junk

endmodule : x

But 7.2 still doesn't like inline (automatic) variable declarations:

for ( int i = 0; i < 32; ++i ) // <-- 'int i' causes ERROR

 

[cms]

Greatest. SystemVerilog looks much attractive than conventional VHDL
\Verilog and even SystemC.
There is only one reason why I haven't started yet synthesable altera
project in SV: I wasn't sure about claimed support SV by the Quartus.

Tell us please, have you got already successful completed at least one
altera's SV project?

Digitally yours,
Michael Tsvetkov

http://www.jpegls.com

On Oct 10, 9:44 am, "Systemv User" <syst...@nowhere.net> wrote:

Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor:

`define SET_REG( x, y ) reg_``y <= x
`define CONCAT( x, y, z ) x``_``y``_``z

assign `CONCAT( bus0, func1, endpoint0 ) = 1'b0;

and named 'end' blocks:

module x;
...
always_comb begin : my_junk

end : my_junk

endmodule : x

But 7.2 still doesn't like inline (automatic) variable declarations:

for ( int i = 0; i < 32; ++i ) // <-- 'int i' causes ERROR

 

[Edmond Coté]

On Oct 10, 1:44 am, "Systemv User" <syst...@nowhere.net> wrote:

But 7.2 still doesn't like inline (automatic) variable declarations:

for ( int i = 0; i < 32; ++i ) // <-- 'int i' causes ERROR

Make sure to submit a bug report. I had evaluated the initial (very
poor) support for SV in 6.1, and their technical support team were
quite responsive. Otherwise, I am curious, what synthesis tool
currently tops the list of supported features? Does anyone support
generatable modports and modport expressions yet?