Quartus II 5.0 Web Edition questions

[bobrics]

Hi,

I am having some trouble with Quartus II, 5.0 build 168 (WEB EDITION).

1. when I am initializing signals, this initialization does not seem to
be visible in Vector Waveform simulation file (simulator that comes
with Quartus II). Sometimes STD_LOGIC takes '1', and sometimes '0'
value from the beginning.
Here is my signal declaration:
SIGNAL dummySIGNAL: STD_LOGIC := '0';

In this case, for one of the signals, it just initializes it to '1'. I
am not doing anything with the signal yet and zoommed in pretty close
to make sure it does not get pulled up by some other logic.

In Xilinx with ModelSIM I didn't have any problems with this kind of
things.

2. How can I extend the length of default simulation (in seconds)? Q2
does not seem to have an intuitive solution for that.

Thank you

 

[Dan NITA]

Use reset for initializing all signals.




-- Reset

if (RST = '1') then

--

sigDummy <= '0';



-- Synchronise with CLK.

elsif (rising_edge(CLK)) then

--

sigDummy <= '1';



end if;






Dan.

 

[andyjien@gmail.com]

bobrics wrote:

2. How can I extend the length of default simulation (in seconds)? Q2
does not seem to have an intuitive solution for that.

In Waveform Editor, go to Edit -> Set End Time to change the length of
the simulation.