Quartus 4.1 VHDL bug?

[Jeroen]

Hi,

I just spent an hour finding out why something didn't work the way it should
work.

This was the culprit:

if pc_reload<='1' then
pc_reg<=instruction;
else
pc_reg<=pc_reg+1;
end if;

Jeroen

--
email adres invalid: remove the dot

 

[Alex Weddell]

I just spent an hour finding out why something didn't work the way it
should
work.

This was the culprit:

if pc_reload<='1' then
pc_reg<=instruction;
else
pc_reg<=pc_reg+1;
end if;

Jeroen,

I think you may mean:

if pc_reload = '1' then

The <= symbol is an assignment rather than a comparison.
So you were attempting to set pc_reload to '1'.

I hope this helps.

Regards,
Alex

 

[Egbert Molenkamp]

Interesting, but the code is legal VHDL!
The condition, in the IF statement, is true when pc_reload is smaller or
equal then '1'
(It is NOT a signal assugnment)

Although the type of pc_reload is not shown I think for the type you used
'0' is smaller then '1' and '1' is equal then '1'. So the condition is, for
synthesis, always true.

I think the design is not simulated before it was synthesised. You would
have noticed that the else part also was not executed.

Try the following complete example. For simulation the output is always
equal to inst1 indpendent of pc_reload and inst2. And that is also what your
synthesis tool will produce .. only wires between inst1 and pc_reg.

Try to simulate this one:
entity demo is
port (pc_reload : bit;
inst1 : integer;
inst2 : integer;
pc_reg : out integer);

end demo;

architecture condition_check of demo is
begin

process(pc_reload, inst1, inst2)
begin
if pc_reload<='1' then
pc_reg<=inst1;
else
pc_reg<=inst2;
end if;
end process;

end condition_check ;

Egbert Molenkamp


"Alex Weddell" <asw101@soton.ac.uk> schreef in bericht
news:cihmns$8j5$1@aspen.sucs.soton.ac.uk...

I just spent an hour finding out why something didn't work the way it
should
work.

This was the culprit:

if pc_reload<='1' then
pc_reg<=instruction;
else
pc_reg<=pc_reg+1;
end if;


Jeroen,

I think you may mean:

if pc_reload = '1' then

The <= symbol is an assignment rather than a comparison.
So you were attempting to set pc_reload to '1'.

I hope this helps.

Regards,
Alex

 

[Jeroen]

"Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl> wrote in message
news:cihrld$6f$1@ares.cs.utwente.nl...

Interesting, but the code is legal VHDL!
The condition, in the IF statement, is true when pc_reload is smaller or
equal then '1'
(It is NOT a signal assugnment)

I was under the impression this was an signal assignment and forgot about
the relational expression <=. It was a simple typo, one you easily look
over. It's the same mistake that often occurs in C with = and == and where
assignment is an operator and not a statement.

I was wondering it this was yet another bug in Quartus because I thought it
was an illegal statement in VHDL. It turns out not to be.

Although the type of pc_reload is not shown I think for the type you used
'0' is smaller then '1' and '1' is equal then '1'. So the condition is,
for
synthesis, always true.

I use std_logic

I think the design is not simulated before it was synthesised. You would
have noticed that the else part also was not executed.

I'm still only simulating, has not seen hardware yet.

 

[Jeroen]

"Alex Weddell" <asw101@soton.ac.uk> wrote in message
news:cihmns$8j5$1@aspen.sucs.soton.ac.uk...

I just spent an hour finding out why something didn't work the way it
should
work.

This was the culprit:

if pc_reload<='1' then
pc_reg<=instruction;
else
pc_reg<=pc_reg+1;
end if;


Jeroen,

I think you may mean:

if pc_reload = '1' then

Yes, that's the culprint, the extraneous <, which was a typo. It happened to

be that the first instructions where 0,1,2,3,4,5,6,7 so the error was not
obvious at first This piece of code is actually a part of a processor and
this is to reload the program counter with a new value to take a branch (two
byte instruction).

Jeroen

 

[Ralf Hildebrandt]

Jeroen wrote:

I just spent an hour finding out why something didn't work the way it should
work.

This was the culprit:

if pc_reload<='1' then
pc_reg<=instruction;
else
pc_reg<=pc_reg+1;
end if;

Take care of

pc_reg<=pc_reg+1;

This can be easily an infinite loop if you change this stuff to a mux.
Make the process synchronous.


Ralf