Quartus 2.2, SOPC builder and leonardo

[Mancini Stephane]

Hi all,
I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2
with Leonardo.
Indeed, I would like to perform a synthesis separated from the Quartus P&R
for a course (I have a limited time and doing the both is far too long).
The idea is to provide students an already synthesized system : they just
have to complete some peripherals so I can pre-synthesize the whole system
, students do synthesize peripherals and the pieces are put together for P&R with quartus.

The problem is that with Quartus 2.2, the VHDL produced by SOPC builder is
synthesized and P&R by Quartus which double the process time.
It's also quite difficult to feed leonardo with the produced VHDL because
it contains Quartus pragmas such as --synthesis read_comments_as_HDL on

So, I have two solutions :
- Perform the synthesis with Quartus and save the result
But how can it be done ? I have'nt seen the corresponding menu

- Perform the synthesis with Leonardo
It would need to remove comments (not difficult with awk) but I would
have to deal with the lpm macros. How can I force leonardo to keep their
names ?

- Extract entities containing pragmas (awk) and leave them for Quartus,
the rest would be synthesized with leonardo. But it would be difficult to manage
the project...

What do you think about that ?

Do you have suggestions ?

FOR ALTERA ENGINEERS : the former solution with separate vhdl files containing lpm
macros was much more easier to deal with.... It's a typical case where upgrade may transform to
downgrade ...


Thanks a lotfor your ideas

 

[Mike Treseler]

Mancini Stephane wrote:

Hi all,
I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2
with Leonardo.
Indeed, I would like to perform a synthesis separated from the Quartus P&R
for a course (I have a limited time and doing the both is far too long).
The idea is to provide students an already synthesized system : they just
have to complete some peripherals so I can pre-synthesize the whole system
, students do synthesize peripherals and the pieces are put together for P&R with quartus.

Consider leaving the sopc code alone.

Write and sim the peripheral code separately in my_wrapper.vhd.
In this code, include an unbound component
instance representing connections to the sopc top level entity.

Compile my_wrapper.vhd in leo to make my_wrapper.edf.
Add my_wrapper.edf to the quartus file list containing the sopc files.


-- Mike Treseler

 

[Mancini Stephane]

Thanks Mike,
That's we are already doing. The problem is that I want to synthesize the
sopc project before and just perform the P&R during the course to speed up the whole
process. So I have to synthesize the sopc project with leonardo or
Quartus. In this later case, is it possible to just perform a synthesis
with Quartus ?
What can I do ?
thanks a lot.

Stéphane


On Mon, 13 Oct 2003 11:17:37 -0700, Mike Treseler wrote:

Mancini Stephane wrote:
Hi all,
I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2
with Leonardo.
Indeed, I would like to perform a synthesis separated from the Quartus P&R
for a course (I have a limited time and doing the both is far too long).
The idea is to provide students an already synthesized system : they just
have to complete some peripherals so I can pre-synthesize the whole system
, students do synthesize peripherals and the pieces are put together for P&R with quartus.


Consider leaving the sopc code alone.

Write and sim the peripheral code separately in my_wrapper.vhd.
In this code, include an unbound component
instance representing connections to the sopc top level entity.

Compile my_wrapper.vhd in leo to make my_wrapper.edf.
Add my_wrapper.edf to the quartus file list containing the sopc files.


-- Mike Treseler

 

[Mike Treseler]

Mancini Stephane wrote:

The problem is that I want to synthesize the
sopc project before and just perform the P&R during the course to speed up the whole
process.

If you set
[Quartus II, Assignments, Settings, Mode, Smart Compilation]

then the P&R is mainly limited to changes from the previous run.

So I have to synthesize the sopc project with leonardo or
Quartus.

Leave the sopc stuff in quartus for synthesis,
unless you want to rewrite it.

In this later case, is it possible to just perform a synthesis
with Quartus ?

Yes, but it is an Altera-only .vqm netlist, not .edf.

[Quartus II, Assignments, Settings, Compiler Settings,
Synthesis, save a node level netlsit]

And Quartus can't do leo's rtl viewer.

You don't need to use leo for your wrapper
file unless you want to.

What can I do ?

You could benchmark the different methods and pick the best:

1. add the leo netlist wrapper.edf to sopc file list
2. add the source files for wrapper.vhd directly to sopc file list
3. use the source files for wrapper.vhd with the quartus netlist sopc.vqm
4. use the leo netlist wrapper.edf with the quartus netlist sopc.vqm

-- Mike Treseler

 

[Peter Sommerfeld]

Stephane,

I hope I understand your question correctly.

As of version 2.7, SOPC Builder allows the synthesis to be performed
by Quartus (called native synthesis). It is settable on the "System
Generation" tab.

I am running ver 3.0, and there is no option at all anymore, so it
ALWAYS gets synthesized by Quartus (SOPC only produces VHDL or
Verilog).

-- Pete

Thanks Mike,
That's we are already doing. The problem is that I want to synthesize the
sopc project before and just perform the P&R during the course to speed up the whole
process. So I have to synthesize the sopc project with leonardo or
Quartus. In this later case, is it possible to just perform a synthesis
with Quartus ?
What can I do ?
thanks a lot.

Stéphane

 

[Vaughn Betz]

"Mancini Stephane" <nospam@nospam.nospam> wrote in message news:<pan.2003.10.14.12.17.57.905341@nospam.nospam>...

Thanks Mike,
That's we are already doing. The problem is that I want to synthesize the
sopc project before and just perform the P&R during the course to speed up the whole
process. So I have to synthesize the sopc project with leonardo or
Quartus. In this later case, is it possible to just perform a synthesis
with Quartus ?
What can I do ?
thanks a lot.

Stéphane

Hi Mancini,

Yes, it is possible.

Go to Assignments->Settings->Synthesis and check "Save a node-level
netlist to a persistant source file (Verilog Quartus Mapping File)".
Give this file some name in the box (say sopc_base.vqm).

Just run synthesis next (Processing->Start->Run Analysis & Synthesis).

You will now have sopc.vqm in your project directory. It is a
flattened, synthesized netlist in structural Verilog, where everything
is made up of Altera primitives that exist on the device.

Next, create a new project where you include this sopc_base.vqm file.
You can now write peripherals in verilog or VHDL (or whatever) and
hook them up to your base SoPC logic. Quartus synthesis will be run
when you compile your total design, but since the sopc_base part of
the design is already synthesized, there will be little to do there
exist hook it into the circuit, so it will save some CPU time.

I doubt it takes very long to synthesize a base SoPC system in any
case, so this may not be worth the effort, but it is an option.

Vaughn