Qn on synthesis of "default" in the case statement

[SB]

All,

I have a question on the "default" branch in a Verilog case
statement. Notice that the following case statement features all
outcomes for the case variable "encoded_signal". There is also a
default statement.

always @ (encoded_signal)
begin
case(encoded_signal)
3'b000: decoded_out = 8'b00000000;
3'b001: decoded_out = 8'b00000001;
3'b010: decoded_out = 8'b00000011;
3'b011: decoded_out = 8'b00000111;
3'b100: decoded_out = 8'b00001111;
3'b101: decoded_out = 8'b00011111;
3'b110: decoded_out = 8'b00111111;
3'b111: decoded_out = 8'b01111111;
default: decoded_out = 8'b11111111;
endcase
end

Since every valid outcome for "encoded_signal" is already accounted
for, will the synthesis tool synthesize the default statement? And if
so how?

Could this lead to redundant logic in the synthesized design?

Regards,
Paul

 

[Jonathan Bromley]

On Sun, 27 Sep 2009 14:32:41 -0700 (PDT), SB wrote:

Notice that the following case statement features all
outcomes for the case variable "encoded_signal".
There is also a default statement.

The default branch covers the 56 possibilities that
you didn't enumerate - containing X or Z values.

always @ (encoded_signal)
begin
case(encoded_signal)
3'b000: decoded_out = 8'b00000000;
3'b001: decoded_out = 8'b00000001;
3'b010: decoded_out = 8'b00000011;
3'b011: decoded_out = 8'b00000111;
3'b100: decoded_out = 8'b00001111;
3'b101: decoded_out = 8'b00011111;
3'b110: decoded_out = 8'b00111111;
3'b111: decoded_out = 8'b01111111;
default: decoded_out = 8'b11111111;
endcase
end

Since every valid outcome for "encoded_signal" is already accounted
for, will the synthesis tool synthesize the default statement?

No. Synthesis understands only 1 and 0 values on bits. It cannot
build logic that tests for X or Z. So, as you say in your
introduction, all possible values for synthesis have been
explicitly enumerated even without the default. Indeed, many
synthesis tools will warn you about the default branch being
ignored.

Could this lead to redundant logic in the synthesized design?

Not in your example, but it's easy to find examples in which
a "default" most certainly DOES give redundant logic - hence
the (ghastly) use of full_case and parallel_case directives
in some synthesisable code, and the motivation for SystemVerilog's
"unique" and "priority" qualifiers for case and if statements.

There are, of course, prettier ways to describe a
thermometer decoder. You might care to consider what
your case statement would look like if there were six
input bits instead of three...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.