Q: 'reg' is a future reserved keyword, parsing as identifier

J

Jason

Guest
I wrote a simple program for a 8-bit counter in Cadence with VerilogA

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
`include "constants.vams"
`include "disciplines.vams"

module counter(clk, reset, result, ena);
input clk;
input reset;
input ena;
output reg [7:0] result;
always @(posedge clk or posedge reset)
begin
if (reset)
result = 0;
else if (ena)
result = result + 1;
end
endmodule
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

When the compiling proceeding, I have several problems which say:

--------------------------------------------------------------------
Warning from spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: Warning: `reg' is a future reserved keyword, parsing
as
identifier.
Error found by spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: "output reg <<--? [7:0] result;"
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: Error: syntax error
Warning from spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 13: Warning: `always' is a future reserved keyword,
parsing as
identifier.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 13: Warning: `posedge' is a future reserved keyword,
parsing as
identifier.
------------------------------------------------------------------------

I tried to search google, but there's no proper answer for this
problem. Anyone has any clue?

Thx

Jay
 
Jason wrote, on 04/06/09 12:48:
I wrote a simple program for a 8-bit counter in Cadence with VerilogA


`include "constants.vams"
`include "disciplines.vams"

module counter(clk, reset, result, ena);
input clk;
input reset;
input ena;
output reg [7:0] result;
always @(posedge clk or posedge reset)
begin
if (reset)
result = 0;
else if (ena)
result = result + 1;
end
endmodule


When the compiling proceeding, I have several problems which say:

--------------------------------------------------------------------
Warning from spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: Warning: `reg' is a future reserved keyword, parsing
as
identifier.
Error found by spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: "output reg <<--? [7:0] result;"
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 11: Error: syntax error
Warning from spectre during SpectreHDL compile.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 13: Warning: `always' is a future reserved keyword,
parsing as
identifier.
"/home/qw/vlsi/Libraries/UMC18_MM_RF/test_sys/counter/veriloga/
veriloga.va",
line 13: Warning: `posedge' is a future reserved keyword,
parsing as
identifier.
------------------------------------------------------------------------

I tried to search google, but there's no proper answer for this
problem. Anyone has any clue?

Thx

Jay
Click to expand...
Jay,

You've created this as a VerilogA view, whereas the code you have entered is
VerilogAMS. VerilogA is a subset of VerilogA which supports Analog behaviour
only, and can be simulated in a pure analog simulator such as spectre.

For VerilogAMS you need a mixed signal simulator. VerilogAMS supports both
digital and analog behaviour.

In fact your module is purely digital, so cannot work in an analog simulator.

Create your view as VerilogAMS and it should work OK.

Best Regards,

Andrew.
 
Jason wrote, on 04/07/09 13:37:
On 6 Apr, 15:09, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm> wrote:
Jay,

You've created this as a VerilogA view, whereas the code you have entered is
VerilogAMS. VerilogA is a subset of VerilogA which supports Analog behaviour
only, and can be simulated in a pure analog simulator such as spectre.

For VerilogAMS you need a mixed signal simulator. VerilogAMS supports both
digital and analog behaviour.

In fact your module is purely digital, so cannot work in an analog simulator.

Create your view as VerilogAMS and it should work OK.

Best Regards,

Andrew.

Hi, Andrew

Yes, this does sort out the problem. But the following question is
when I'm doing the mixed-signal simulation, an error is reported as
following:

"Verilog-XL Executable 'verilog.vmx' cannot be located from $PATH.
Please specify correct location in Digital Simulation Options."

However, I couldn't find the ' verilog.vmx' in my local drives. So how
can I solve this problem?

Thx
Click to expand...
Jason,

If you want to use VerilogAMS, then you'll need to use AMS Designer (the
simulator is "ams" in ADE). You must have picked "spectreVerilog" which is the
old mixed signal simulator. With that you can use pure digital views (you'd
have to pick "verilog" as the view type (or something like that).

To run either the newer AMS simulator or spectreVerilog (aka "verimix"), you'll
need to have an IUS installation (e.g. IUS82) in your UNIX path. For example, in
my case verilog.vmx is in <IUSinstDir>/tools/bin which is in my path. Similarly
ncsim is in the same place (and this is what AMS uses).

You might want to read the documentation on AMS simulation (including the AMS
quickstart) in the IUS installation.

Regards,

Andrew.
 
On 6 Apr, 15:09, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm> wrote:
Jay,

You've created this as a VerilogA view, whereas the code you have entered is
VerilogAMS. VerilogA is a subset of VerilogA which supports Analog behaviour
only, and can be simulated in a pure analog simulator such as spectre.

For VerilogAMS you need a mixed signal simulator. VerilogAMS supports both
digital and analog behaviour.

In fact your module is purely digital, so cannot work in an analog simulator.

Create your view as VerilogAMS and it should work OK.

Best Regards,

Andrew.
Click to expand...
Hi, Andrew

Yes, this does sort out the problem. But the following question is
when I'm doing the mixed-signal simulation, an error is reported as
following:

"Verilog-XL Executable 'verilog.vmx' cannot be located from $PATH.
Please specify correct location in Digital Simulation Options."

However, I couldn't find the ' verilog.vmx' in my local drives. So how
can I solve this problem?

Thx
 
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