Q: 'helper' library to go with OVL?

[Erik Seligman]

I've noticed that when using the OVL assertion language,
designers tend to write a lot of instrumentation code
along with the assertions. For example, an assertion
might require using the value of signal A from two cycles
before the arrival of signal B, so they will add an extra
'always' block to create a signal A_2_cycles_ago.

What I'm wondering is if anyone has tried to put together
a helper macro library to go with OVL, to enable common
types of this instrumentation to be created in a cleaner
way. It looks to me like a lot of designers reinvent the
same wheels.

I'd be curious to hear either about free/open efforts, or
products for sale from CAD vendors.

(And yes, I do know about better assertion languages like
PSL or SVA!)




---------------------------------------------------------------------------
Erik Seligman, eseligma@aracnet.com
Speaking for myself, not Intel or Aracnet.

 

[Swapnajit Mittra]

Hi,

Since you already mentioned about SVA and PSL, probably another way
of looking into this question with your specific example is: which
one of the two is preferable - to define an operator (such as ##)
or write a parameterized module or function that does the same
(or, to cite a simpler example, do we prefer a+b or add(a,b)).
Since Verilog can not define an operator (or 'overload' it), the
only way would be to define a function or module (a la OVL).
IIRC, there are known cases from computer science literatures
when an operator is mandatorily required and a function template
will not do. This is probably one of the motivations behind
introducing those operators in the assertion languages.

- Swapnajit.

--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.co­m
For subscribing to the mailing list:
<URL: http://www.project-veripage.co­m/list/?p=subscribe&id=1>