Q:Altera's excalibur device

[algous]

Dear all,
I implement a DMA controller in the PLD side of the ALtera's
excalibur device(epxa1), and a block ram in the PLD other. DMA
controller access data through the PLD-to-STRIP bridge. I config the
DMA controller through STRIP-to-PLD bridge.
now I need to exchange datas between the sdram(out of chip) and the
RAM in PLD. It seemed that some datas not translated successly, there
would be eight continual beats failed every since. while other datas
sucessful, and there would be eight continual beats as well.
The DMA controller was designed refer to ALtera's "AN 287: Using
Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
AN287 is ok, I thinked it's worked well.
In the other hand, If the DMA controller exchange between the
SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
controller worked very well. The timing and function simulation is
successed as well.
I think if there were some bugs in the excliabur device. The above
sympton seemd is related with the SDRAM' controller or the AHB BUS.
because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
to the memory are made up of eight-beat reads and writes. A request
from the system bus that does not map directly to this fixed-beat
access(for example, A larger burst size or a wrapping transfer) is
handled by performing multiple accesses. Burst termination is utilized
to maximize throughput."

regards

algous

 

[Mike Lewis]

Did you try simulating the problem to see if
you can get more information. Your description
of the problem is rather high level.

Mike

"algous" <algous2002@yahoo.com.cn> wrote in message
news:1e71fcd5.0312081757.40fea000@posting.google.com...

Dear all,
I implement a DMA controller in the PLD side of the ALtera's
excalibur device(epxa1), and a block ram in the PLD other. DMA
controller access data through the PLD-to-STRIP bridge. I config the
DMA controller through STRIP-to-PLD bridge.
now I need to exchange datas between the sdram(out of chip) and the
RAM in PLD. It seemed that some datas not translated successly, there
would be eight continual beats failed every since. while other datas
sucessful, and there would be eight continual beats as well.
The DMA controller was designed refer to ALtera's "AN 287: Using
Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
AN287 is ok, I thinked it's worked well.
In the other hand, If the DMA controller exchange between the
SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
controller worked very well. The timing and function simulation is
successed as well.
I think if there were some bugs in the excliabur device. The above
sympton seemd is related with the SDRAM' controller or the AHB BUS.
because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
to the memory are made up of eight-beat reads and writes. A request
from the system bus that does not map directly to this fixed-beat
access(for example, A larger burst size or a wrapping transfer) is
handled by performing multiple accesses. Burst termination is utilized
to maximize throughput."

regards

algous

 

[algous]

hi Mike,
At present, the function and timing simulating are all well. data
translated as expectation.


"Mike Lewis" <someone@microsoft.com> wrote in message news:<MsqdnTiwDoZz_0qiRVn-sQ@magma.ca>...

Did you try simulating the problem to see if
you can get more information. Your description
of the problem is rather high level.

Mike

"algous" <algous2002@yahoo.com.cn> wrote in message
news:1e71fcd5.0312081757.40fea000@posting.google.com...
Dear all,
I implement a DMA controller in the PLD side of the ALtera's
excalibur device(epxa1), and a block ram in the PLD other. DMA
controller access data through the PLD-to-STRIP bridge. I config the
DMA controller through STRIP-to-PLD bridge.
now I need to exchange datas between the sdram(out of chip) and the
RAM in PLD. It seemed that some datas not translated successly, there
would be eight continual beats failed every since. while other datas
sucessful, and there would be eight continual beats as well.
The DMA controller was designed refer to ALtera's "AN 287: Using
Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
AN287 is ok, I thinked it's worked well.
In the other hand, If the DMA controller exchange between the
SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
controller worked very well. The timing and function simulation is
successed as well.
I think if there were some bugs in the excliabur device. The above
sympton seemd is related with the SDRAM' controller or the AHB BUS.
because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
to the memory are made up of eight-beat reads and writes. A request
from the system bus that does not map directly to this fixed-beat
access(for example, A larger burst size or a wrapping transfer) is
handled by performing multiple accesses. Burst termination is utilized
to maximize throughput."

regards

algous

 

[Howard Butler @ Altera]

Hello,

Just for clarification, it sounds like you are attempting to design a
DMA controller in the FPGA of an Excalibur(XA)device and you are
currently having problems accessing SDRAM via the following path:

FPGA DMA -> PLD-to-Stripe Bridge -> AHB2 Bus -> SDRAM Controller AHB2
Slave interface-> Off chip SDRAM

It also sounds like you were SUCCESSFUL in accessing the embedded
stripe SRAM blocks via the following path:

FPGA DMA -> PLD-to-Stripe Bridge -> AHB2 Bus -> SRAM AHB2 Slave
interface -> Embedded Stripe SRAM.

If you are able to access SRAM successfully and are NOT able to access
SDRAM, problem is more than likely either in your SDRAM controller
setup, or a board level problem.


SDRAM Controller Setup:

With most SDRAM controllers there is some initial setup that has to
occur before you can access it properly. The SDRAM controller in the
embedded stripe is no different. The XA tool flow provides flow that
can make this very easy for you. The last page of the stripe
megawizard is where the memory map for the device is configured. In
addition, the configuration information for the SDRAM chips that your
using can be loaded. There are several SDRAM chips that the stripe
megawizard knows about and you can just select the chip that you are
using. If the chip that you are using isn't in the megawizard, then
you can add your own custom settings. The parameters entered to the
wizard will eventually get passed to the XA bootloader and it will
configure the SDRAM controller for you according the parameters you
entered in the megawizard. If you are not using the XA bootloader, or
just want to know what is involed in SDRAM configuration, AN141 Using
the SDRAM Controller, discusses details of SDRAM configuration.

You can get that here: http://www.altera.com/literature/an/an141.pdf
In addition, because SDRAM configuration is something that mostly done
during the boot process, I would recommend that you also have a look
at AN187 Booting Excalibur devices
http://www.altera.com/literature/an/an187.pdf.

Board Level Problem:

If you are not using a XA development board, then there is a
possiblity that you my have a board layout problem. AN141 also gives
some basic SDRAM layout guidelines.

One common layout mistake people make with SDR and XA is not feeding
back the SD_CLK_N to the SD_DQS[0] pin. See page 28 of AN141. XA
SDRAM controller is both an DDR and SDR controller and in the SDR
configuration, SD_CLK_N needs to be feedback to SD_DQS[0].

One other thing you should look at:

So by being able to access SRAM it sounds like you are faily close to
getting your DMA to work. One other thing you could consider is
downloading a SDRAM model for the chip you are using and attempt to
simulate your system. AN192 has a SDR Micron model and shows both the
processor and a master in the FPGA accessing SDRAM. So this will give
you a good proof of concept of SDRAM Access to look at.

You can get it here: http://www.altera.com/literature/an/an192.pdf.
There are also design files which you can get from the top level of
the literture page: http://www.altera.com/literature/lit-exc.jsp

Finally on the statement in the HRM:

"Transfers
to the memory are made up of eight-beat reads and writes. A request
from the system bus that does not map directly to this fixed-beat
access(for example, A larger burst size or a wrapping transfer) is
handled by performing multiple accesses. Burst termination is
utilized
to maximize throughput."

This is basically referring to how the backend access to SDRAM are
made. The SDRAM controller is going to buffer information that is
written/read when accessing the SDRAM controller. The frequency and
amount of data retrived from SDRAM is going to depend on the type of
SDRAM configuration you have laided out on your board. For
example...If you are interfacing to 16-bit sdram a request from XA
which is 32 bits will take multiple accesses to complete to account
for the mis-match in data widths.

I hope this helps...

God Bless
-Howard



algous2002@yahoo.com.cn (algous) wrote in message news:<1e71fcd5.0312081757.40fea000@posting.google.com>...

Dear all,
I implement a DMA controller in the PLD side of the ALtera's
excalibur device(epxa1), and a block ram in the PLD other. DMA
controller access data through the PLD-to-STRIP bridge. I config the
DMA controller through STRIP-to-PLD bridge.
now I need to exchange datas between the sdram(out of chip) and the
RAM in PLD. It seemed that some datas not translated successly, there
would be eight continual beats failed every since. while other datas
sucessful, and there would be eight continual beats as well.
The DMA controller was designed refer to ALtera's "AN 287: Using
Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
AN287 is ok, I thinked it's worked well.
In the other hand, If the DMA controller exchange between the
SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
controller worked very well. The timing and function simulation is
successed as well.
I think if there were some bugs in the excliabur device. The above
sympton seemd is related with the SDRAM' controller or the AHB BUS.
because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
to the memory are made up of eight-beat reads and writes. A request
from the system bus that does not map directly to this fixed-beat
access(for example, A larger burst size or a wrapping transfer) is
handled by performing multiple accesses. Burst termination is utilized
to maximize throughput."

regards

algous