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Dave_V
Guest
Thanks in advance.
Can someone who is familiar with Python explain the advantages of
writing complex simulation models ( to mix in with Verilog ) in
languages such as SystemVerilog or Vera instead of Python? I don't
know these languages, but I just wrote a complex model for the IBM
PowerPC '440 peripheral bus, then ran the exact same Python code on
the 440 itself when the prototype came in. Is any 'higher' simulation
language so portable that it would have run both on Windows 2000 for
simulation and also on the PowerPC target running Linux? Would I have
to pay for twice for the language? ( compared to 0$ for Python? ). And
also, do these languages have extensive libraries for general
computational tasks? Good string manipulation? Equivalents of Python's
lists and dictionaries? Platform independent GUI capability like the
Tk interface?
Can someone who is familiar with Python explain the advantages of
writing complex simulation models ( to mix in with Verilog ) in
languages such as SystemVerilog or Vera instead of Python? I don't
know these languages, but I just wrote a complex model for the IBM
PowerPC '440 peripheral bus, then ran the exact same Python code on
the 440 itself when the prototype came in. Is any 'higher' simulation
language so portable that it would have run both on Windows 2000 for
simulation and also on the PowerPC target running Linux? Would I have
to pay for twice for the language? ( compared to 0$ for Python? ). And
also, do these languages have extensive libraries for general
computational tasks? Good string manipulation? Equivalents of Python's
lists and dictionaries? Platform independent GUI capability like the
Tk interface?