Puzzling warning message

[garyr]

I've written some Verilog for an Altera EPM1270 CPLD; I'm using the web
version of Quartus II 11.0. When I compile this code the fitter generates
the following message:

Info: Carry-chain of 30 logic cells and starting on logic cell
"CMP_UD_FO_udividend[0]" could not be split into legal LABs. Carry
feedthrough logic cells will be inserted into the chain in order to make it
legal
Info: List of logic cells in the chain (ordered from chain start to end)
Info: Node "CMP_UD_FO_udividend[0]"
...
Info: Node "CMP_UD_FO_udividend[29]"

I haven't yet tested this code in a device but it behaves OK when simulated
using the web version of ModelSim. The Fitter summary indicates that 89% of
the total logic elements were required.

Is this something I should be concerned about? Could I eliminate this
situation by changing my code in some way?

 

[Gabor]

garyr wrote:

I've written some Verilog for an Altera EPM1270 CPLD; I'm using the web
version of Quartus II 11.0. When I compile this code the fitter generates
the following message:

Info: Carry-chain of 30 logic cells and starting on logic cell
"CMP_UD_FO_udividend[0]" could not be split into legal LABs. Carry
feedthrough logic cells will be inserted into the chain in order to make it
legal
Info: List of logic cells in the chain (ordered from chain start to end)
Info: Node "CMP_UD_FO_udividend[0]"
...
Info: Node "CMP_UD_FO_udividend[29]"

I haven't yet tested this code in a device but it behaves OK when simulated
using the web version of ModelSim. The Fitter summary indicates that 89% of
the total logic elements were required.

Is this something I should be concerned about? Could I eliminate this
situation by changing my code in some way?



As I read this message, your carry chain spans multiple LAB's and that

means that you will have som additional delay each time it crosses into
a new LAB. If after all that, the design still meets timing, then you
can ignore the message. If not, you have an idea where to look for
design changes to improve timing, for example breaking up the 30-bit
operation into smaller pieces with hand coded look-ahead carry logic.
If this operation (which appears to be a magnitude comparison) can
be replaced with something simpler (like an equality comparison) then
you could also improve the timing and ease the placement requirements.

-- Gabor

 

[glen herrmannsfeldt]

Gabor <gabor@szakacs.invalid> wrote:

garyr wrote:
(snip)

Info: Carry-chain of 30 logic cells and starting on logic cell
"CMP_UD_FO_udividend[0]" could not be split into legal LABs. Carry
feedthrough logic cells will be inserted into the chain in order to
make it legal

(snip)

As I read this message, your carry chain spans multiple LAB's and that
means that you will have som additional delay each time it crosses into
a new LAB. If after all that, the design still meets timing, then you
can ignore the message. If not, you have an idea where to look for
design changes to improve timing, for example breaking up the 30-bit
operation into smaller pieces with hand coded look-ahead carry logic.

Or pipeline the carry between the pieces.

It used to be that the internal carry logic was fast enough,
even at 30 bits, that you couldn't beat it with any look-ahead
carry logic. Maybe that isn't true anymore.

-- glen

 

[garyr]

Gabor, glen,

Thanks very much for your replies. I'm very much a novice HDL user so your
suggestions are far beyond my capabilities to implement. Speed is not an
issue so I'm happy to learn that I'm safe to just ignore this message.

Best regards,
Gary Richardson

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:jheer3$23i$2@speranza.aioe.org...

Gabor <gabor@szakacs.invalid> wrote:
garyr wrote:
(snip)

Info: Carry-chain of 30 logic cells and starting on logic cell
"CMP_UD_FO_udividend[0]" could not be split into legal LABs. Carry
feedthrough logic cells will be inserted into the chain in order to
make it legal

(snip)
As I read this message, your carry chain spans multiple LAB's and that
means that you will have som additional delay each time it crosses into
a new LAB. If after all that, the design still meets timing, then you
can ignore the message. If not, you have an idea where to look for
design changes to improve timing, for example breaking up the 30-bit
operation into smaller pieces with hand coded look-ahead carry logic.

Or pipeline the carry between the pieces.

It used to be that the internal carry logic was fast enough,
even at 30 bits, that you couldn't beat it with any look-ahead
carry logic. Maybe that isn't true anymore.

-- glen