pure structural design

[Francisco]

Hi, I'm using at the university a Cadence software that only accepts
structural VHDL code as input.
I would like to know if there is a way to convert RTL or behavioral code
into pure structural code (up to gate level). I guess this would imply to
synthetise the original code and in some way convert that gate level output
to structural VHDL code.
If someone knows something like this I would really appreciate it. I'm
totally lost at this, I can't find information but I guess it should be
possible to do.
Thank you

Francisco

 

[Francisco]

Tim Hubberstey wrote:

You're guess is correct, you need a synthesis tool to do this. You will
need to have your source in RTL form as behavioural is (usually) not
synthesizable. The structural code you refer to is often called a
(gate-level) netlist and most synthesizers will give you options for the
output format. Common formats are EDIF, Verilog, VHDL, and usually some
kind of proprietary vendor format. The synthesizer will also output an
SDF file which is used to back-annotate estimated delays onto the
netlist for simulation.

You will also need a device library for the kind of chip you are
targeting. Libraries are usually specific to a synthesis tool.

Thank you Tim, I would like to make two more questions.

1. I've found that quartus has an option to output .vho files, is this what
I need?, what software do you recomend for what I need?

2. Since my ultimate goal is to make a layout of the circuit, not an FPGA,
I'm not sure what library should I use. I would like to use something that
doesn't have any restrictions, since I don't have a target device with
limitations on number of gates and such. I would make the necessary
primitives (logic gates?) by hand on Cadence. Does such library exist?

 

[Francisco]

Tim Hubberstey wrote:

I haven't used Quartus for a while so I don't remember which extensions
mean what. In any case, you can't use Quartus for what you want because
the output will be targeted for an FPGA and the gate-level primitives
are totally different from those found in an ASIC.

The software you will need will be determined by what is available to
you at your school. ASIC synthesis tools are VERY expensive (10's of
thousands of dollars). Device libraries usually come from a chip vendor
and are only supplied if they feel there is a reasonable chance of a
sale. Your best bet is to talk to your academic advisors and find out
what resources you have access to.

That's hard to hear, I was hoping I would be able to do it with free
software. Just curiosity, what programs are able to do it?

 

[Francisco]

Tim Hubberstey wrote:

Again, I stress that you should talk to someone at your school about
this. You can't be the first student to have run into this issue.

In fact, I believe I am, there isn't much development on these topics on my
university (and in my country)
I'm doing this for my thesis. I've already knew the program that you pointed
and it doesn't compile RTL VHDL. In fact I tried a lot of programs I've
found in the FAQ. Nonetheless, I appreaciate a lot your help.
Now I've found Alliance (http://www-asim.lip6.fr/recherche/alliance/), it
looks promising.

 

[Tim Hubberstey]

Francisco wrote:

Hi, I'm using at the university a Cadence software that only accepts
structural VHDL code as input.
I would like to know if there is a way to convert RTL or behavioral code
into pure structural code (up to gate level). I guess this would imply to
synthetise the original code and in some way convert that gate level output
to structural VHDL code.

You're guess is correct, you need a synthesis tool to do this. You will
need to have your source in RTL form as behavioural is (usually) not
synthesizable. The structural code you refer to is often called a
(gate-level) netlist and most synthesizers will give you options for the
output format. Common formats are EDIF, Verilog, VHDL, and usually some
kind of proprietary vendor format. The synthesizer will also output an
SDF file which is used to back-annotate estimated delays onto the
netlist for simulation.

You will also need a device library for the kind of chip you are
targeting. Libraries are usually specific to a synthesis tool.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Tim Hubberstey]

Francisco wrote:

Tim Hubberstey wrote:

You're guess is correct, you need a synthesis tool to do this. You will
need to have your source in RTL form as behavioural is (usually) not
synthesizable. The structural code you refer to is often called a
(gate-level) netlist and most synthesizers will give you options for the
output format. Common formats are EDIF, Verilog, VHDL, and usually some
kind of proprietary vendor format. The synthesizer will also output an
SDF file which is used to back-annotate estimated delays onto the
netlist for simulation.

You will also need a device library for the kind of chip you are
targeting. Libraries are usually specific to a synthesis tool.


Thank you Tim, I would like to make two more questions.

1. I've found that quartus has an option to output .vho files, is this what
I need?, what software do you recomend for what I need?

2. Since my ultimate goal is to make a layout of the circuit, not an FPGA,
I'm not sure what library should I use. I would like to use something that
doesn't have any restrictions, since I don't have a target device with
limitations on number of gates and such. I would make the necessary
primitives (logic gates?) by hand on Cadence. Does such library exist?

I haven't used Quartus for a while so I don't remember which extensions
mean what. In any case, you can't use Quartus for what you want because
the output will be targeted for an FPGA and the gate-level primitives
are totally different from those found in an ASIC.

The software you will need will be determined by what is available to
you at your school. ASIC synthesis tools are VERY expensive (10's of
thousands of dollars). Device libraries usually come from a chip vendor
and are only supplied if they feel there is a reasonable chance of a
sale. Your best bet is to talk to your academic advisors and find out
what resources you have access to.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Mike Treseler]

Francisco wrote:

1. I've found that quartus has an option to output .vho files, is this what
I need?

No, a .vho file is a vhdl netlist of Altera FPGA primitives
that is used for timing simulation.

2. Since my ultimate goal is to make a layout of the circuit, not an FPGA,
I'm not sure what library should I use. I would like to use something that
doesn't have any restrictions, since I don't have a target device with
limitations on number of gates and such. I would make the necessary
primitives (logic gates?) by hand on Cadence. Does such library exist?

It is the synthesis library written by the ASIC vendor for
your synthesis software. Until you know what your target
device and synthesis tool will be, consider writing
and simulating generic RTL code. This will consume most of
your time, in any case.

-- Mike Treseler

 

[Tim Hubberstey]

Francisco wrote:

Tim Hubberstey wrote:

I haven't used Quartus for a while so I don't remember which extensions
mean what. In any case, you can't use Quartus for what you want because
the output will be targeted for an FPGA and the gate-level primitives
are totally different from those found in an ASIC.

The software you will need will be determined by what is available to
you at your school. ASIC synthesis tools are VERY expensive (10's of
thousands of dollars). Device libraries usually come from a chip vendor
and are only supplied if they feel there is a reasonable chance of a
sale. Your best bet is to talk to your academic advisors and find out
what resources you have access to.


That's hard to hear, I was hoping I would be able to do it with free
software. Just curiosity, what programs are able to do it?

The most commonly used is probably Synopsys Design Compiler, the
cheapest is probably Synplicity ASIC. Since you already have access to
some Cadence tools, you should see if you also have access to their
synthesizer (I believe the name of the tool is Encounter).

There may be some free tools available but they probably won't fit into
the "commercial" design flow. This means that time spent learning them
may not lead to "useful" knowledge of how commercial tools work. One
tool that looks interesting is
http://www.staticfreesoft.com/index.html
Note that I haven't used this at all but the home page looks like it
might do something like what you want. You should also check out the
comp.lang.vhdl FAQ at
http://www.eda.org/comp.lang.vhdl/

Again, I stress that you should talk to someone at your school about
this. You can't be the first student to have run into this issue.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Rob Dekker]

"Francisco" <fran575@mailandnews.com> wrote in message news:326r83F3hdvjlU1@individual.net...

Tim Hubberstey wrote:

I haven't used Quartus for a while so I don't remember which extensions
mean what. In any case, you can't use Quartus for what you want because
the output will be targeted for an FPGA and the gate-level primitives
are totally different from those found in an ASIC.

The software you will need will be determined by what is available to
you at your school. ASIC synthesis tools are VERY expensive (10's of
thousands of dollars). Device libraries usually come from a chip vendor
and are only supplied if they feel there is a reasonable chance of a
sale. Your best bet is to talk to your academic advisors and find out
what resources you have access to.

That's hard to hear, I was hoping I would be able to do it with free
software. Just curiosity, what programs are able to do it?

Hi Francisco,

Verific builds synthesis front-ends for commercial EDA tools.
We translate RTL to gate-level, and you can write the gate-level netlist out in
a veriety of formats (including VHDL structural).
That is exactly what you need.

We sell our software in source code form, but the binary evaluation copy is free.
We normally don't mail that out if we don't know where it goes to (you would not
believe how many requests we get from very dubious sources), but I can make
an exception if you only use the software for your thesis work at your University.

Go to www.verific.com and fill out the request form for an evaluation license.
Send a request to info@verific.com if you get a rejection email, and mention
this text.

Rob Dekker