pullups

[ujku]

HI all,

I want to write the following configuration in verilog or
systemverilog:
2 tristate buffers which drives a certain wire A.
both bufferes have the same enable signal expect that it is inverted
in one of the buffers. additionaly the wire A is puuledup with
something like this

pullup pw(A);

The problem is that this doesnt allow to the buffers to drive a low
level on that wire. In that case i get X on my simulation.

Ayn workaround about this configuration?

Regards
Elvis

 

[Jonathan Bromley]

On Tue, 9 Sep 2008 23:41:24 -0700 (PDT), ujku wrote:

I want to write the following configuration in verilog or
systemverilog:
2 tristate buffers which drives a certain wire A.
both bufferes have the same enable signal expect that it is inverted
in one of the buffers. additionaly the wire A is puuledup with
something like this

pullup pw(A);

The problem is that this doesnt allow to the buffers to drive a low
level on that wire. In that case i get X on my simulation.

Really? If your 3-state drivers are of the default "strong"
driving strength, there should be no problem.

This works fine for me:

module tristate (input choose, d0, d1, output y);
assign y = choose ? d1 : 1'bz;
assign y = choose ? 1'bz : d0;
pullup pu_y;
endmodule

However, you don't need the pullup because your tristate
enable is simply acting as a multiplexer. This is
just as good, faster to simulate and more synthesis-friendly:

assign y = choose ? d1 : d0;
--
Jonathan Bromley, Consultant

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