pullup on array of wires?

[Mark McDougall]

I have an array of wires...

ie. wire [31:0] foo;

Is there an easy way to 'pullup' the entire array?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Jonathan Bromley]

On Fri, 15 Jun 2007 15:43:07 +1000, Mark McDougall <markm@vl.com.au>
wrote:

I have an array of wires...

ie. wire [31:0] foo;

Not truly an array of wires, but rather a 32-bit vector...

Is there an easy way to 'pullup' the entire array?

assign (pull1, pull0) foo = -1;

You could, I suppose, generate an array of pullup
primitives, but the assign is way easier.

No promises about whether this would work in synthesis -
depends on your tool, and of course it's likely that the
appropriate device resources exist only on I/O pads.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

Mark McDougall wrote:

I have an array of wires...

ie. wire [31:0] foo;

Is there an easy way to 'pullup' the entire array?

Jonathan's approach works, but I don't know whether a synthesis tool
will handle it correctly.

His alternate suggestion of an array of pullup instances would look
like

pullup p[31:0](foo);

Or you could just change the net from a wire to a tri1, a net type
that has an implicit pullup.

 

[Jonathan Bromley]

On Fri, 15 Jun 2007 10:02:02 -0700, sharp@cadence.com wrote:

an array of pullup instances would look like

pullup p[31:0](foo);

<blush> I had completely forgotten that it's legal to
create an instance array of primitives, just as it is
for modules. I had also completely forgotten about tri1...

Or you could just change the net from a wire to a tri1, a net type
that has an implicit pullup.

Hmmm. Secrets of the Gate-level Modelling Masters. I suspect
that the pullup() primitive, and tri1, are at least as likely
to give synthesis a hard time as my continuous assign.

What never fails to astonish me, though, is how useful this
obscure [*] gate/switch-level Verilog stuff can be when
you're doing board-level models. Pullups, "tranif" primitives
to model metal-to-metal switches and jumper links, module path
delays, trireg, timing checks - they all have their uses in
board-level modelling.

[*] Obscure to me. Yes, I know it's at the core of
Verilog's heritage. But I'm an RTL guy at heart
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kevin Neilson]

sharp@cadence.com wrote:

Mark McDougall wrote:
I have an array of wires...

ie. wire [31:0] foo;

Is there an easy way to 'pullup' the entire array?

Jonathan's approach works, but I don't know whether a synthesis tool
will handle it correctly.

His alternate suggestion of an array of pullup instances would look
like

pullup p[31:0](foo);

Or you could just change the net from a wire to a tri1, a net type
that has an implicit pullup.

I like to use tri1, but it won't work for synthesis--at least not with
the FPGA tools I use. In that case, you have to instantiate the PULLUP
primitive for each bit. I'm not sure why the tri1 can't be recognized.
In FPGAs, the only place pullups may be used is usually only in the IOB.

 

[Mark McDougall]

sharp@cadence.com wrote:

Mark McDougall wrote:

ie. wire [31:0] foo;
Is there an easy way to 'pullup' the entire array?

Jonathan's approach works, but I don't know whether a synthesis tool
will handle it correctly.

His alternate suggestion of an array of pullup instances would look
like
pullup p[31:0](foo);

OK, thanks for the suggestions guys! I'm more familiar with VHDL but our
testbench is written in Verilog - BTW this is purely for simulation, no
synthesis required...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266