pss analysis of PLL

R

rexer

Guest
Hello
I was performing the pss simulation but some problems occured.
Let me describe my system.
I'm making PLL which consists:
Reference voltage (square wave-vpulse): 4MHz
PFD/CP: 3 state, transitor level
Loop Filter: second order (R+C) || C
VCO (sinusoid): 300 MHz (Verilog-A example from Cadence 'pllLib')
Block to change vco sin to square and sent it to Divider.
Divider: N=79 (Verilog-A example from "Hidden State in SpectreRF" by
Ken Kundert)

(I have also transistor level divider and VCO which are working but
first I wanted to make pnoise simulation with these two ideal Verilog-
A models to save the time)

So, the transient simulation shown that PLL locks and the the
stabilization time is 10us.
Then I set the following parameters of PSS and Pnoise analysyis:
PSS:
Beat frequency: 4MHz (like desired frequency od out signal of divider)
Nr of harmonics: 79
Accuracy Defaults: moderate
Additional time for stabilization: 10us
(rest of parameters is default. The 'Oscillator' option is not
checked)

Ok, when I run the pss simulation it was working until 10us. Then I
noticed the convNorm was quite big like 27.2e+03 and the analysis was
making loops. Nothing more happend so I had too stop the simulation.

So there is a problem with convergence. But in transient analysis the
ripples of VCO control voltage, after 10us, were like 1mV which means
100kHz variation of VCO frequency (Kvco=100MHz/V). So there shouldn't
be any problem.

So my question is:
Are the pss settings correct?

Thanks in advance for replies.
 
Hi,

Your problem is a bit tricky since it worked at transistor level but
not with the verilog-A models.
These are few things I was thinking of:
1. Have you tried to simulate the Divider and the VCO on their own to
cross-check the functionality ?
2. When I simulate oscillators using PSS, I tend to higher a bit the
beat frequency, I thought it was helping the convergence. I don't
recall setting the Additional time for stabilization. I think I was
leaving it blank.
3. Nowadays, PSS comes with two solvers, A time domain one (shooting)
or a Harmonic balance. Have you ever tried to switch back and forth
between them ?

That's all what I can say about this rather difficult problem for me.
Have you ever looked at the Cadence's application notes on simulating
PLLs with Spectre RF ? You might consider looking at the Designer's
Guide forum as well.

BTW, best way to supply your Cadence/MMSIM (Spectre) versions is to
provide the outputs of the following UNIX commands:
UNIX> icfb -W
UNIX> spectre -W

That's all I can help with I'm afraid ...

Cheers
Riad.
 
On May 18, 3:09 am, Riad KACED <riad.ka...@gmail.com> wrote:
Hi,

Your problem is a bit tricky since it worked at transistor level but
not with the verilog-A models.
These are few things I was thinking of:
1. Have you tried to simulate the Divider and the VCO on their own to
cross-check the functionality ?
2. When I simulate oscillators using PSS, I tend to higher a bit the
beat frequency, I thought it was helping the convergence. I don't
recall setting the Additional time for stabilization. I think I was
leaving it blank.
3. Nowadays, PSS comes with two solvers, A time domain one (shooting)
or a Harmonic balance. Have you ever tried to switch back and forth
between them ?

That's all what I can say about this rather difficult problem for me.
Have you ever looked at the Cadence's application notes on simulating
PLLs with Spectre RF ? You might consider looking at the Designer's
Guide forum as well.

BTW, best way to supply your Cadence/MMSIM (Spectre) versions is to
provide the outputs of the following UNIX commands:
UNIX> icfb -W
UNIX> spectre -W

That's all I can help with I'm afraid ...

Cheers
Riad.
Click to expand...
or loose the pss converge condition (there're some parameters can be
played with), or using qpss simulation
 
Hi
The version of spectre is 6.0.1.127.
I think I didn't write it clearly. In my case pss analysis cannot
converage in both transistor level circuit and circuit with ideal VCO
i Freq Divider.
I just consider making this simulation first in the second mentioned
model because of time saving.

I made an additional test. I put DC Voltage at the input of VCO to
force generaing signal with fixed frequency N (divider ratio) times
bigger than referece frequency. And in this case pss could converage.
It means that I must improve my loop filter to achieve smaller ripples
of its output signal. But as I said before these ripples weren't big.

I tried the qpss analysis but since it requires at least two
fundamental tones I did't know exactly how to set its parameters.

Do you know how to configure the qpss analysis? And if you know how to
change the convergence settings in pss analysis, it would be helpful.
 
rexer wrote, on 05/19/09 15:28:
Hi
The version of spectre is 6.0.1.127.
I think I didn't write it clearly. In my case pss analysis cannot
converage in both transistor level circuit and circuit with ideal VCO
i Freq Divider.
I just consider making this simulation first in the second mentioned
model because of time saving.

I made an additional test. I put DC Voltage at the input of VCO to
force generaing signal with fixed frequency N (divider ratio) times
bigger than referece frequency. And in this case pss could converage.
It means that I must improve my loop filter to achieve smaller ripples
of its output signal. But as I said before these ripples weren't big.

I tried the qpss analysis but since it requires at least two
fundamental tones I did't know exactly how to set its parameters.

Do you know how to configure the qpss analysis? And if you know how to
change the convergence settings in pss analysis, it would be helpful.
Click to expand...
qpss doesn't make sense here. This is a single tone simulation - the reference
frequency. I'm assuming you've not set oscillator (it said that in your original
post, so I'm just re-confirming) - a PLL is a driven circuit.

Check that your PFD doesn't have any dead bands - these can cause trouble (I
think Ken's paper talks about this).

You may need longer for it to settle, maybe.

I think shooting is more likely to be successful than harmonic balance - you are
likely to need a very large number of harmonics for harmonic balance to work.

Best Regards,

Andrew.
 
Hello

I was trying to perform the pss analysis of my PLL but I got an error:
insufficient amount of memory. So because for a short time I have a
possibility of using virtuoso version is IC1.6.1.3 I decided to try
cadence new tool to simulate PLLs.

I was trying to extract the VCO macro model. I was following the
spectre user guide 7.0.1 instructions but I had problem with the step
8:

8. Run the simulation with the VCO extraction plugin.
Using the plugin for VCO extraction, the command line is
spectre –plugin libpllPPVoscModel_sh.so

I wrote the mentioned command in the command line of Virtuoso but an
error appeard:
Error eval: unbound variable -plugin

Mayby this command should be written somewhere else. Maybe in some
cadence config file, just to let the program know that I want load
that plugin. I don't know.

Could you give me some hints how can I solve this problem.

Thanks in advance for reply.
 
ok, I found the solution

I had to add parameter ppv eg. ppv=20 to PSS or PNOISE. It means the
number of sample points per period.
 
On 6$B7n(B6$BF|(B, $B8aA0(B12:56, rexer <blazej_nowa...@tlen.pl> wrote:
ok, I found the solution

I had to add parameter ppv eg. ppv=20 to PSS or PNOISE. It means the
number of sample points per period.
Click to expand...
Hi rexer,

I'm facing probably same situation where you were in. Pls describe
where I should put "ppv=20" parameter.
Thx in advance,
Naoya
 
Hi rexer,

Im facing with probably same situation where you used to be in. Pls
explain more detailed about where you put "ppv=20" in.

Thx in advance.
 
Hello

Actually, when I was tring to make the extraction of tha VCO first
time I had to add this parameter to in PNOISE -> options -> additional
parameters. But, when I was making it second time I noticed that in
PNOISE -> options there is a field "enalbel osc ppv", which is checked
by default, so I didn't need to use any additionally parameters.
Ealier, there wasn't this field, and until now I don't know if I did
something wrong first time.

The best ideal is follow the spectre user guide and have hope that
everything will be ok ;-)
Btw, first time I made the extraction of single output VCO and I
couldn't measure the PSD of phase noise of the output of the PLL.
Although I add the block vco_freq in the PLL_bench after transient
analysis in Results -> Direct Plot -> Main Form I couldnt plot PLL
noise PSD.
When I tried with two output VCO it started to work ;-)

Now I'm curious about one thing.
I made the extraction of VCO. Then I made transient analysis of
generated model and I noticed that at the VCO output (eg. "osc_p") the
signal is a square wave.
I would like to know if this is correct. Mayby this aproximation works
like this.
Pls write what waveform you have.
 
在 2009年5月14日星期四UTC+8上午1时37分11秒，rexer写道：
Hello
I was performing the pss simulation but some problems occured.
Let me describe my system.
I'm making PLL which consists:
Reference voltage (square wave-vpulse): 4MHz
PFD/CP: 3 state, transitor level
Loop Filter: second order (R+C) || C
VCO (sinusoid): 300 MHz (Verilog-A example from Cadence 'pllLib')
Block to change vco sin to square and sent it to Divider.
Divider: N=79 (Verilog-A example from "Hidden State in SpectreRF" by
Ken Kundert)

(I have also transistor level divider and VCO which are working but
first I wanted to make pnoise simulation with these two ideal Verilog-
A models to save the time)

So, the transient simulation shown that PLL locks and the the
stabilization time is 10us.
Then I set the following parameters of PSS and Pnoise analysyis:
PSS:
Beat frequency: 4MHz (like desired frequency od out signal of divider)
Nr of harmonics: 79
Accuracy Defaults: moderate
Additional time for stabilization: 10us
(rest of parameters is default. The 'Oscillator' option is not
checked)

Ok, when I run the pss simulation it was working until 10us. Then I
noticed the convNorm was quite big like 27.2e+03 and the analysis was
making loops. Nothing more happend so I had too stop the simulation.

So there is a problem with convergence. But in transient analysis the
ripples of VCO control voltage, after 10us, were like 1mV which means
100kHz variation of VCO frequency (Kvco=100MHz/V). So there shouldn't
be any problem.

So my question is:
Are the pss settings correct?

Thanks in advance for replies.
Click to expand...

PSS+PNOISE simulation for PLL is not feasible due to the convergence difficulty encountered in PSS, especially when the divide ration is large. If you really want to see the phase noise performance of a PLL, you can try transient noise instead. However, the simulation time might be very long.
 
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