PSOC3/5

[rickman]

Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et.
al.?

I guess I'm wondering if they will be discussed here much.

Rick

 

[-jg]

On Sep 10, 1:11 am, rickman <gnu...@gmail.com> wrote:

Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et.
al.?

I guess I'm wondering if they will be discussed here much.

Rick

First, they have to become 'real'

You could include the Actel Fusion in the same space ?

The PSCOx logic is at the base-end, so they are Logic Augmented
processors, not processor augmented logic.

I actually worked up some test designs in PSOC, but we have paused
that path until Cypress prove real devices, _and_ sensible prices.
(and faster Sw would be nice too...)

Meanwhile, Nuvoton have released some 3-5V, low cost M0 core
MicroControllers, which expand our options.

-jg

 

[rickman]

On Sep 9, 5:46 pm, -jg <jim.granvi...@gmail.com> wrote:

On Sep 10, 1:11 am, rickman <gnu...@gmail.com> wrote:

Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et.
al.?

I guess I'm wondering if they will be discussed here much.

Rick

First, they have to become 'real'

You could include the Actel Fusion in the same space ?

The PSCOx logic is at the base-end, so they are Logic Augmented
processors, not processor augmented logic.

I actually worked up some test designs in PSOC, but we have paused
that path until Cypress prove real devices, _and_ sensible prices.
(and faster Sw would be nice too...)

 Meanwhile, Nuvoton have released some 3-5V, low cost M0 core
MicroControllers, which expand our options.

-jg

Are you the jmg that talks about Nuvoton in the PSOC developer
forums?

Yeah, I agree that you can't ship vaporware. As to price, what I have
seen of the Fusion part, I won't have any sockets that have enough
cash for those parts. I seem to recall $40 each. That's twice what I
spend on a large MCU and a small FPGA.

Rick

 

[-jg]

On Sep 10, 12:04 pm, rickman <gnu...@gmail.com> wrote:

On Sep 9, 5:46 pm, -jg <jim.granvi...@gmail.com> wrote:



On Sep 10, 1:11 am, rickman <gnu...@gmail.com> wrote:

Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et.
al.?

I guess I'm wondering if they will be discussed here much.

Rick

First, they have to become 'real'

You could include the Actel Fusion in the same space ?

The PSCOx logic is at the base-end, so they are Logic Augmented
processors, not processor augmented logic.

I actually worked up some test designs in PSOC, but we have paused
that path until Cypress prove real devices, _and_ sensible prices.
(and faster Sw would be nice too...)

 Meanwhile, Nuvoton have released some 3-5V, low cost M0 core
MicroControllers, which expand our options.

-jg

Are you the jmg that talks about Nuvoton in the PSOC developer
forums?

IIRC, jg was taken

Yeah, I agree that you can't ship vaporware.  As to price, what I have
seen of the Fusion part, I won't have any sockets that have enough
cash for those parts.  I seem to recall $40 each.  That's twice what I
spend on a large MCU and a small FPGA.

Yes, but they do show a smaller sibling coming on the road map - which
could have a more tolerable price ?

-jg

 

[Bryan]

Avnet is currently shipping a Spartan-6/PSoC3 development board. The
PSoC 3 is used for several system management functions -- enabling
regulators, programmable clock to the FPGA, USB/UART bridge, slave
serial configuration of the FPGA, Flash programming, touch-sensitive
buttons, driving an LCD, dynamically measuring the voltage/current/
power on three supply rails, I2C interface to a fuel gauge. None of
these functions were done explicitly in the programmable logic. The
processor peripherals themselves are highly configurable, with a mix
of digital and analog capabilities.

This board uses engineering sample part CY8C3866AXI-040ES2, which
shows as in stock at the Cypress store -- http://www.cypress.com/?mpn=CY8C3866AXI-040ES2.
I believe the errata affecting this ES2 device are posted publicly.
I'm told that production on this device is imminent.

www.em.avnet.com/spartan6lx16-evl

Regards,
Bryan
Avnet


On Sep 9, 10:26 pm, -jg <jim.granvi...@gmail.com> wrote:

On Sep 10, 12:04 pm, rickman <gnu...@gmail.com> wrote:



On Sep 9, 5:46 pm, -jg <jim.granvi...@gmail.com> wrote:

On Sep 10, 1:11 am, rickman <gnu...@gmail.com> wrote:

Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et..
al.?

I guess I'm wondering if they will be discussed here much.

Rick

First, they have to become 'real'

You could include the Actel Fusion in the same space ?

The PSCOx logic is at the base-end, so they are Logic Augmented
processors, not processor augmented logic.

I actually worked up some test designs in PSOC, but we have paused
that path until Cypress prove real devices, _and_ sensible prices.
(and faster Sw would be nice too...)

 Meanwhile, Nuvoton have released some 3-5V, low cost M0 core
MicroControllers, which expand our options.

-jg

Are you the jmg that talks about Nuvoton in the PSOC developer
forums?

IIRC, jg was taken

Yeah, I agree that you can't ship vaporware.  As to price, what I have
seen of the Fusion part, I won't have any sockets that have enough
cash for those parts.  I seem to recall $40 each.  That's twice what I
spend on a large MCU and a small FPGA.

Yes, but they do show a smaller sibling coming on the road map - which
could have a more tolerable price ?

-jg

 

[rickman]

On Sep 9, 11:24 pm, Bryan <bryan.fletc...@avnet.com> wrote:

Avnet is currently shipping a Spartan-6/PSoC3 development board.  The
PSoC 3 is used for several system management functions -- enabling
regulators, programmable clock to the FPGA, USB/UART bridge, slave
serial configuration of the FPGA, Flash programming, touch-sensitive
buttons, driving an LCD, dynamically measuring the voltage/current/
power on three supply rails, I2C interface to a fuel gauge.  None of
these functions were done explicitly in the programmable logic.  The
processor peripherals themselves are highly configurable, with a mix
of digital and analog capabilities.

This board uses engineering sample part CY8C3866AXI-040ES2, which
shows as in stock at the Cypress store --http://www.cypress.com/?mpn=CY8C3866AXI-040ES2.
I believe the errata affecting this ES2 device are posted publicly.
I'm told that production on this device is imminent.

www.em.avnet.com/spartan6lx16-evl

Regards,
Bryan
Avnet

That seems rather bizarre. These boards are done in conjunction with
the chip vendors, no? I would expect Xilinx to never want to be part
of the same promotion as a Cypress PSOC. That wouldn't be a lot
different from sharing a board with Altera or better, an Actel Fusion
part!

I didn't know the PSOC had digital interfaces other than one used to
boot the chip, I2C I seem to recall. The others are all done in the
programmable digital section I thought.

What sort of programmable clock to the FPGA? I don't recall seeing a
decent PLL on the PSOC. I guess they can take the main clock and
divide it down in a counter. But that would be pretty lame. If I
need to generate clock rates to the FPGA, I would want more than one
and each one to come from a PLL. But even the real FPGAs don't have
"real" PLLs that can work with a wide range of input and output clock
rates. Cypress makes some clock chips that do that much better, but I
guess that technology is just not compatible with FPGA processes.

The clock I would really like to see on the PSOC is one that will let
a 32.768 kHz, low power osc set the rate for the very low power (< 2
uW) battery backed up RTC and also serve as reference for the PLL to
generate the main clocks. I've seen that on just one or two MCUs to
date. An older Atmel ARM MCU even had special I/O to put the system
into low power mode, not just the MCU and be taken back out. That was
a real, real time clock!

Rick

 

[Bryan]

I really don't consider a Xilinx FPGA and Cypress PSoC to be competing
technologies, and I think Cypress and Xilinx would agree with me. The
programmable logic inside the PSoC is more similar to CPLD logic, and
the FPGA doesn't have the analog capability of the PSoC. On this
project, the FPGA and PSoC were quite complementary. All of the
things that we did with the PSoC are things that the FPGA couldn't do
on its own, and the PSoC doesn't have a large amount of programmable
logic and related cores and IP, which is why we wanted the FPGA.

For example, here are a few things we did with the PSoC that we
couldn't do with the FPGA alone:
- USB interface
- Touch sensitive buttons
- Dynamic power measurement of the system power rails
- Direct drive of a custom segment LCD
- Suspend/Hibernate control of the FPGA

Likewise, here are a few things we did with the Spartan-6 that we
couldn't do with the PSoC:
- Interface to an LPDDR SDRAM (S6 supports up to DDR3)
- Embedded ethernet MAC interfaced to external PHY
- Interface to 100+ I/Os on the FMC connector
- Any number of programmable logic functions that require more than
the equivalent logic in ~200 CPLD macrocells
- High performance DSP
- Native TMDS/HDMI output
- High-speed differential signalling
- VHDL

I think they are both interesting and useful chips to have in your
toolbox when considering the needs of your project.

I'm not sure about your request for the 32.768 kHz osc, but I will
look into it.

Bryan

That seems rather bizarre.  These boards are done in conjunction with
the chip vendors, no?  I would expect Xilinx to never want to be part
of the same promotion as a Cypress PSOC.  That wouldn't be a lot
different from sharing a board with Altera or better, an Actel Fusion
part!

I didn't know the PSOC had digital interfaces other than one used to
boot the chip, I2C I seem to recall.  The others are all done in the
programmable digital section I thought.

What sort of programmable clock to the FPGA?  I don't recall seeing a
decent PLL on the PSOC.  I guess they can take the main clock and
divide it down in a counter.  But that would be pretty lame.  If I
need to generate clock rates to the FPGA, I would want more than one
and each one to come from a PLL.  But even the real FPGAs don't have
"real" PLLs that can work with a wide range of input and output clock
rates.  Cypress makes some clock chips that do that much better, but I
guess that technology is just not compatible with FPGA processes.

The clock I would really like to see on the PSOC is one that will let
a 32.768 kHz, low power osc set the rate for the very low power (< 2
uW) battery backed up RTC and also serve as reference for the PLL to
generate the main clocks.  I've seen that on just one or two MCUs to
date.  An older Atmel ARM MCU even had special I/O to put the system
into low power mode, not just the MCU and be taken back out.  That was
a real, real time clock!

Rick- Hide quoted text -

- Show quoted text -

 

[rickman]

You don't need to tell me what the PSOC can do. I am very aware of
how the original PSOC was logic limited. But the PSOC3/5 is much less
so. They may not have tons of logic on them, but Xilinx doesn't just
sell FPGAs, they also sell CPLDs. The PSOC3/5 will compete very
effectively against an MCU/FPGA/analog combination and in fact, that
is exactly the market they are looking to capture.

As to the combination being useful, I am sure there are a very few
applications where you might want to use a PSOC3/5 in conjunction with
an FPGA. But you are not really taking full advantage of the PSOC3/5
at that point and these will be rare applications.

The real concern is that Cypress is opening a market for the combo
chips that Xilinx has no real experience with. I expect Xilinx is
keeping their nose to the wind on this and will jump in if they see it
as a significant market. Personally, I see integrated devices like
this as the next "big" thing. Let's face it. The need for larger
FPGAs is diminishing as they have reached nearly a million LUTs (not
withstanding the Xilinx inflation factor). The number of designs that
need such large devices is getting to be a small fraction of the total
market and the FPGA makers want to get their chips in general consumer
items. MCUs are fine, but it is hard to do everything in software
sometimes. So a device with a combination of software and
programmable hardware will be the cutting edge for these new, low
price markets.

If Xilinx is really as smart as they should be, I can't imagine they
don't have something like a PSOC3/5 in the wings. I expect they are
waiting for Cypress and Actel to open the market for them. Then they
will come in like the 600 lb gorilla and sit where they wish.

Rick

On Sep 14, 10:25 pm, Bryan <bryan.fletc...@avnet.com> wrote:

I really don't consider a Xilinx FPGA and Cypress PSoC to be competing
technologies, and I think Cypress and Xilinx would agree with me. The
programmable logic inside the PSoC is more similar to CPLD logic, and
the FPGA doesn't have the analog capability of the PSoC. On this
project, the FPGA and PSoC were quite complementary. All of the
things that we did with the PSoC are things that the FPGA couldn't do
on its own, and the PSoC doesn't have a large amount of programmable
logic and related cores and IP, which is why we wanted the FPGA.

For example, here are a few things we did with the PSoC that we
couldn't do with the FPGA alone:
- USB interface
- Touch sensitive buttons
- Dynamic power measurement of the system power rails
- Direct drive of a custom segment LCD
- Suspend/Hibernate control of the FPGA

Likewise, here are a few things we did with the Spartan-6 that we
couldn't do with the PSoC:
- Interface to an LPDDR SDRAM (S6 supports up to DDR3)
- Embedded ethernet MAC interfaced to external PHY
- Interface to 100+ I/Os on the FMC connector
- Any number of programmable logic functions that require more than
the equivalent logic in ~200 CPLD macrocells
- High performance DSP
- Native TMDS/HDMI output
- High-speed differential signalling
- VHDL

I think they are both interesting and useful chips to have in your
toolbox when considering the needs of your project.

I'm not sure about your request for the 32.768 kHz osc, but I will
look into it.

Bryan

That seems rather bizarre. These boards are done in conjunction with
the chip vendors, no? I would expect Xilinx to never want to be part
of the same promotion as a Cypress PSOC. That wouldn't be a lot
different from sharing a board with Altera or better, an Actel Fusion
part!

I didn't know the PSOC had digital interfaces other than one used to
boot the chip, I2C I seem to recall. The others are all done in the
programmable digital section I thought.

What sort of programmable clock to the FPGA? I don't recall seeing a
decent PLL on the PSOC. I guess they can take the main clock and
divide it down in a counter. But that would be pretty lame. If I
need to generate clock rates to the FPGA, I would want more than one
and each one to come from a PLL. But even the real FPGAs don't have
"real" PLLs that can work with a wide range of input and output clock
rates. Cypress makes some clock chips that do that much better, but I
guess that technology is just not compatible with FPGA processes.

The clock I would really like to see on the PSOC is one that will let
a 32.768 kHz, low power osc set the rate for the very low power (< 2
uW) battery backed up RTC and also serve as reference for the PLL to
generate the main clocks. I've seen that on just one or two MCUs to
date. An older Atmel ARM MCU even had special I/O to put the system
into low power mode, not just the MCU and be taken back out. That was
a real, real time clock!

Rick- Hide quoted text -

- Show quoted text -