Providing FPGA-specific evaluation IP

[Brad]

Hi All,

I want to provide evaluation versions of my IP, targeted at Xilinx,
Altera, etc., without giving out the VHDL source.

AFAIK, I can synthesize to netlist and distribute the netlist, and the
netlist will cover at least a family of parts. Are there any guides
available to get me started?

-Brad

 

[OutputLogic]

Hi Brad,

Have you considered mangling your source code.It provides less
protection comparing to netlist, but might be sufficient in your case.
I've seen at least one large semiconductor company that distributed
their IP cores that way.
VCS has -Xmangle option to do that. There are other tools to do VHDL
mangling/obfuscation.

Thanks,
Evgeni