Protel : ERC floating input error everywhere !

D

dave

Guest
Hello,

Could somebody please give me a hint on what to do about the ERC
analysis in Protel99SE giving me "floating input" errors in ALL my
input pins connected to a BUS. For example, a memomory address bus
connected to the address pins in the part, they all give me this
error. I have the "Electrical grid" enabled, and I have redrawn the
wire from the bus tap to the pin over and over, I see the "bubble" for
the electrical grid. I can move the part with the mouse (and pressing
CTRL key), and all the wires move with the part, which makes me think
that all wires are correctly connected to the pins.

I also have the "snap grid" enabled, and so the connection between
the bus tap and the pin is a straight line.

The part in the library has the right "Electrical type" setting for
all the pins. Address pins are "input," Data lines are "I/O," Control
lines are "Input," and VCC and GND are all "power." I tried updating
the part from the library, and also updating the part from the cache
in the schematic.

Any idea, hint or comment is appreciated.

Thanks in advance

David
 
On 30 Jan 2004 10:27:36 -0800, tecnico@nsstc.uah.edu (dave) wrote:

Hello,

Could somebody please give me a hint on what to do about the ERC
analysis in Protel99SE giving me "floating input" errors in ALL my
input pins connected to a BUS. For example, a memomory address bus
connected to the address pins in the part, they all give me this
error. I have the "Electrical grid" enabled, and I have redrawn the
wire from the bus tap to the pin over and over, I see the "bubble" for
the electrical grid. I can move the part with the mouse (and pressing
CTRL key), and all the wires move with the part, which makes me think
that all wires are correctly connected to the pins.

I also have the "snap grid" enabled, and so the connection between
the bus tap and the pin is a straight line.

The part in the library has the right "Electrical type" setting for
all the pins. Address pins are "input," Data lines are "I/O," Control
lines are "Input," and VCC and GND are all "power." I tried updating
the part from the library, and also updating the part from the cache
in the schematic.

Any idea, hint or comment is appreciated.

Thanks in advance

David
Click to expand...
Ummm, this might be an oversight on my part, but you did assign net
names to each pin connected to the buss didn't you?. Even though you
have a physical wire connected to a buss, you also need to specify
what the pin is by providing a Net label.

-Beau Schwabe
 
David,
Besides Beau's comments the other issue could be that there is nothing
driving the other end of the bus? This could be due to an error keeping your
bus connections floating on that segment of the design. If your busses are
correctly designated and connected they will provide a driving signal from
the address source chip(s) outputs. If the source chip is not there or the
bus has any discontinuity you will not have the drive for your input address
line inputs. Somewhere you are missing the connection to the driving
chip(s). Study the "Help" on correctly making bus connections between chips
and between sheets. Somewhere I suspect that your bus is disconnected which
could be a net naming issue, a bus naming issue or bus port issue.

--
Sincerely,
Brad Velander

"Beau Schwabe" <bschwabe@atlanta.nsc.com> wrote in message
news:401aa84c.13756899@usenet.nsc.com...
On 30 Jan 2004 10:27:36 -0800, tecnico@nsstc.uah.edu (dave) wrote:

Hello,

Could somebody please give me a hint on what to do about the ERC
analysis in Protel99SE giving me "floating input" errors in ALL my
input pins connected to a BUS. For example, a memomory address bus
connected to the address pins in the part, they all give me this
error. I have the "Electrical grid" enabled, and I have redrawn the
wire from the bus tap to the pin over and over, I see the "bubble" for
the electrical grid. I can move the part with the mouse (and pressing
CTRL key), and all the wires move with the part, which makes me think
that all wires are correctly connected to the pins.

I also have the "snap grid" enabled, and so the connection between
the bus tap and the pin is a straight line.

The part in the library has the right "Electrical type" setting for
all the pins. Address pins are "input," Data lines are "I/O," Control
lines are "Input," and VCC and GND are all "power." I tried updating
the part from the library, and also updating the part from the cache
in the schematic.

Any idea, hint or comment is appreciated.

Thanks in advance

David

Ummm, this might be an oversight on my part, but you did assign net
names to each pin connected to the buss didn't you?. Even though you
have a physical wire connected to a buss, you also need to specify
what the pin is by providing a Net label.

-Beau Schwabe
Click to expand...
 
Thank you for your answers.

I posted a new question earlier before I could look at your answers.
Unfortunately it took about 2 hours for Google to list my question and
your answers. Where did you guys read/answer to this post? Because you
answered even before I could see my own post.

Anyway,

1. Yes, I forgot to mention that I do have labels for all wires
comming out from the bus.

2. The problem seems to be with the source of the bus, like you
suggested.

I am using the "complex hierarchy" design, and so it appears that
the bus connecting to the sheet symbol is also not connected
correctly. Unfortunately my whole design is based on using multiple
"sheet symbols" and I connected the buses with by assigning them "net
labels" instead of connecting them directly. I have so many sheet
symbols sharing one bus that it is very impractical to connect the bus
directly to each.

But still, I tried connecting the bus directly to at least one of
the sheet symbols, and I still an ERC error, however, it doesn't come
with any description.

I have more than 15 pages, all with complex hierarchy this way, so,
it's taking me a while to propagate the changes from level to level
and try to run the ERC again.

Thanks in advance again.


David
 
Dave,
Ok, now I am sure now that your busses are not connecting. The bus ports
will not connect automagically between sheet symbols. I mainly used to used
a flat hierarchy in Protel but I believe with all of my heart that your
problem is the missing Bus connections between your sheet symbols. Also at
fault could be your bus naming convention, it must follow the ADDR(0..15)
type format with the matching individual signals labeled ADDR0, ADDR1,
ADDR2, etc..
There is a not too well announced fact with Protel, if you use a complex
hierarchy then you must use a complex hierarchy throughout and all sheet
symbol ports must be connected by busses or wires where each is appropriate.
As well with the complex hierarchies you have to connect the port symbols
between all sheet symbols. Not long ago I tried to add a sheet symbol into
an already filled page to add some modifications to a circuit, figuring I
could just mix the flat hierarchy that I already had with the complex
hierarchy for the new sheet additions. Not a chance in the world, I either
had all my connectivity in the flat hierarchy or I had my connectivity with
the sheet symbol section but never would the two meet. Would have been nice
if both systems could have coexisted.

As for the speed of newsgroup messages, it all depends on how often the
newsgroup server you use does it's checks for new messages. I have noted
that Google seems to be very slow, I once waited about 12 - 16 hours for one
of my messages to show up in Google.

--
Sincerely,
Brad Velander

"dave" <engineer_soul@yahoo.com> wrote in message
news:ab662096.0401301451.6f9e7f03@posting.google.com...
Thank you for your answers.

I posted a new question earlier before I could look at your answers.
Unfortunately it took about 2 hours for Google to list my question and
your answers. Where did you guys read/answer to this post? Because you
answered even before I could see my own post.

Anyway,

1. Yes, I forgot to mention that I do have labels for all wires
comming out from the bus.

2. The problem seems to be with the source of the bus, like you
suggested.

I am using the "complex hierarchy" design, and so it appears that
the bus connecting to the sheet symbol is also not connected
correctly. Unfortunately my whole design is based on using multiple
"sheet symbols" and I connected the buses with by assigning them "net
labels" instead of connecting them directly. I have so many sheet
symbols sharing one bus that it is very impractical to connect the bus
directly to each.

But still, I tried connecting the bus directly to at least one of
the sheet symbols, and I still an ERC error, however, it doesn't come
with any description.

I have more than 15 pages, all with complex hierarchy this way, so,
it's taking me a while to propagate the changes from level to level
and try to run the ERC again.

Thanks in advance again.


David
Click to expand...
 
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