Protel: Complex hierarchy and buses

[dave]

v.Protel99SE with SP1

Anyone with expierence using "complex hierarchy" in Protel (and using
buses in between)?

I would appreciate any insight or helpful comment about this. I
apologize for the long text of this post, I'm just trying to provide
details that I would ask myself in similar cases.

I have multiple sheet symbols, some are sharing buses (like a mem.
data bus), and some other buses are a straight 1-to-1 connection from
sheet to sheet. But no matter what, the ERC marks all the buses with
errors and the Netlist shows that there really is no connectivity
between these ports. For each symbol's port, it assigns a 'net name'
and never connects that net anywhere. So, if 'symbol A' has output
port D_out(0:5), 'symbol B' has por D_in(0:5), and there is a bus
symbol (thick wire) connecting these two; the netlist assigns net
label "N001" to D_out(0:5), and label "N0043" to D_in(0:5), and these
two never connect to each other. In contrast to ports connecting to a
single wire, the netlist does connect these two with the same net
label.

Port D_out in symbol A is defined as "output," and port D_in in symbol
B is defined as "input." Inside the sheet for each symbol, the
direction of these buses is reversed: D_out is input and D_in is
output. I used to not have these reversed, but I noticed they have to
be reversed, I am very sure this is ok. In fact, when creating the
sheet from the symbol (top-down design), Protel reverses the direction
of the ports.

I have tried renaming the buses and the ports on the symbols and on
the sheets to a common name in between sheets. For example, instead of
D_In and D_out, I renamed the ports (and internal sheet buses) to
"DATA," hopping that I could set the scope to "Global Ports" and get
connectivity by name. This didn't seem to work either.

For running the ERC or creating the Netlist, I have tried doing it
with my complex hierarchy and also with the design flattened. I have
tried setting the scope to "Sheet symbol / Port Connections," and also
to "Only Ports Global." Not matter what, these buses never get
connected.

So, how can I get bus connectivity between sheet symbols ? Should the
ports be named the same ? Should there be a bus symbol connecting
these or would the connection be made by name association ?



Thanks in advance.

David

 

[Brad Velander]

David,
Again I can only suggest that you read all of the manual sections on bus
naming, connections and ports. There are also (or used to be) a PDF tutorial
on the Protel website, try their Knowledgebase section.
From your description I can see that you are naming two sections of the
same bus by different names but then expecting them to connect (D_in to
D_out, won't work), the names must be the same. Even if you connect a bus
line between those two points it still won't connect. A bus line in Protel
is simply a graphic symbol that carries no connectivity except by properly
naming the bus line and bus structure at all points.

Sorry there are no shortcuts, read all of the available materials. You
can also try experimenting with a couple of simple sheets and simple buses,
you will soon get the hang of it.

Oh, I also noted that you are not naming your individual wires that
connect to the bus, if you were they would not have names like N0001 and
N0002. The wires must be labeled similarly to the bus to which they connect,
i.e. D_out0, D_out1, D_out2, etc. connect to Bus D_out(0:5). Don't take my
comments here too literally, I don't recall 100% if the bus name uses ()
brackets or [] brackets, do the numbers go (0:5) or (5:0), etc., check the
documentation.

--
Sincerely,
Brad Velander

"dave" <engineer_soul@yahoo.com> wrote in message
news:ab662096.0402031224.1ad07640@posting.google.com...

v.Protel99SE with SP1

Anyone with expierence using "complex hierarchy" in Protel (and using
buses in between)?

I would appreciate any insight or helpful comment about this. I
apologize for the long text of this post, I'm just trying to provide
details that I would ask myself in similar cases.

I have multiple sheet symbols, some are sharing buses (like a mem.
data bus), and some other buses are a straight 1-to-1 connection from
sheet to sheet. But no matter what, the ERC marks all the buses with
errors and the Netlist shows that there really is no connectivity
between these ports. For each symbol's port, it assigns a 'net name'
and never connects that net anywhere. So, if 'symbol A' has output
port D_out(0:5), 'symbol B' has por D_in(0:5), and there is a bus
symbol (thick wire) connecting these two; the netlist assigns net
label "N001" to D_out(0:5), and label "N0043" to D_in(0:5), and these
two never connect to each other. In contrast to ports connecting to a
single wire, the netlist does connect these two with the same net
label.

Port D_out in symbol A is defined as "output," and port D_in in symbol
B is defined as "input." Inside the sheet for each symbol, the
direction of these buses is reversed: D_out is input and D_in is
output. I used to not have these reversed, but I noticed they have to
be reversed, I am very sure this is ok. In fact, when creating the
sheet from the symbol (top-down design), Protel reverses the direction
of the ports.

I have tried renaming the buses and the ports on the symbols and on
the sheets to a common name in between sheets. For example, instead of
D_In and D_out, I renamed the ports (and internal sheet buses) to
"DATA," hopping that I could set the scope to "Global Ports" and get
connectivity by name. This didn't seem to work either.

For running the ERC or creating the Netlist, I have tried doing it
with my complex hierarchy and also with the design flattened. I have
tried setting the scope to "Sheet symbol / Port Connections," and also
to "Only Ports Global." Not matter what, these buses never get
connected.

So, how can I get bus connectivity between sheet symbols ? Should the
ports be named the same ? Should there be a bus symbol connecting
these or would the connection be made by name association ?



Thanks in advance.

David

 

[dave]

Mr. Velander,

Thank you for your time and comments on all my questions so far.

I apologize if I am repeating myself here. Again, I'm just providing
details.

In the complex hierarchy model that I am using, inside each
schematic sheet, all the wires hooked into a bus are named accordingly
( data0, data1, dataX... for data(0:X) bus -- and yes, the correct
syntax for the bus is with parentheses (x:x) ) . On the parent sheets
for these schematics, I use sheet symbols to represent each of these
schematics. These sheet symbols have ports for buses and wires coming
in/out of the schematic. All I am trying to do in this parent sheet is
to connect the output bus from one schematic into the input bus for
another schematic.

I have gone through the manual several times, and the manual points
out a verbal example (just as a comment) about the advantage of using
complex hierarchy design in projects like a two-channel speaker (left
and right). That is very similar to what I am doing because I have a
sheet that I use multiple times (one for each channel, several
channels total). So, for example, a DAC may have an input bus of 16
bits and output of one or two lines (1 wire each). So, according to
the complex hierarchy model, I could use this DAC multiple times by
just laying out the schematics for it once. And so, in the parent
sheet that distributes the buses to each DAC copy, each bus going to a
DAC has to be named individually (ex. DATA_A(0:5), DATA_B(0:15) ..
etc.), but the input port on the DAC's symbol sheet for that bus, is
named with a generic term (ex. DATA(0:15)). They can't be named
exactly as the bus on the parent sheet because I would have to change
the port on the sheet for the DAC, but there is only 1 original sheet
for the DAC, and the rest are just shortcuts to the original until I
flatten out the design. So, I am looking for a way to connect the bus
on the parent sheet to the bus port on the DAC's sheet symbol by
drawing a bus symbol in between. I have tried putting a 'net name' to
this bus, but the ERC marks the 'net name' to be unconnected. I have
tried just a straight bus symbol with no 'net label', but the inputs
to the DAC appear all to be 'floatting' after I run the ERC.

I have other cases when the bus name remains the same across all
sheets, and so the bus on the parent and the children sheets is named
the same. But I also have the same connectivity problem inside the
children.


Thanks in advance.

David



"Brad Velander" <spamthis@nowhere.com> wrote in message news:<n5VTb.270$G74.203@clgrps13>...

David,
Again I can only suggest that you read all of the manual sections on bus
naming, connections and ports. There are also (or used to be) a PDF tutorial
on the Protel website, try their Knowledgebase section.
From your description I can see that you are naming two sections of the
same bus by different names but then expecting them to connect (D_in to
D_out, won't work), the names must be the same. Even if you connect a bus
line between those two points it still won't connect. A bus line in Protel
is simply a graphic symbol that carries no connectivity except by properly
naming the bus line and bus structure at all points.

Sorry there are no shortcuts, read all of the available materials. You
can also try experimenting with a couple of simple sheets and simple buses,
you will soon get the hang of it.

Oh, I also noted that you are not naming your individual wires that
connect to the bus, if you were they would not have names like N0001 and
N0002. The wires must be labeled similarly to the bus to which they connect,
i.e. D_out0, D_out1, D_out2, etc. connect to Bus D_out(0:5). Don't take my
comments here too literally, I don't recall 100% if the bus name uses ()
brackets or [] brackets, do the numbers go (0:5) or (5:0), etc., check the
documentation.

--
Sincerely,
Brad Velander

 

[dave]

I appreciate the helpful comments. Thank you.

I know what the problem was, I'm just putting this here for the record
in case someone else has this problem.

I was 100% sure that the correct syntax for naming buses was with
parenthesis and colon, like BUS(0:11). Turns out that I needed to use
brackets and '..' instead, like BUS[0..11] . It still confuses me
because I have seen other designs using the parentheses syntax and
apparently they worked O.K. because boards have been correctly built
based on those projects before; however, those projects didn't use the
complex hierarchy model that I am using, that's the only thing I can
think of.

But anyway, that was the main problem. And furthermore, the bus has to
have a 'net label' at the source (from the component or part where it
is created), and a 'net label' at the destination (the bus going into
the pins for another component); it is not enough to have the port
connecting to the bus be named the same way (like D[0..X]). So, if the
bus entries are named D0,D1,D2; the bus label will be D[0..X]

For multisheet connectivity: buses connect to ports, the port does not
necessarily have to be named the same as the bus. When connecting
ports between sheet symbols in a parent sheet, if the bus symbol is
directly connecting the ports, it does not need a 'net label'; if it
is not directly connecting the ports, it needs the 'net label' at the
destination (the label being the same name as the source port) -- even
if the ports are named the same way because the scope of the 'complex
hierarchy' design does not take ports to be global.

Hope it helps someone avoid all the frustration and waste of time that
I experienced.

David

 

[Brad Velander]

David,
Glad you are finding the resolve to your issues.

On the old designs with the parentheses, they probably worked because the
designs were not complex hierarchies. Remember that I told you the bus lines
are just graphical objects and the connections are maintained by using the
correct bus naming only. Now in a flat hierarchy a person would typically
make all net connections global when generating their netlist and thus the
connections were maintained by all the individual netnames on each
individual wire where they joined the bus. In that case the parentheses are
probably just treated as a character in a netname, however the bus was not
required because of the nets global option. If the nets were not global then
the erroneous bus name would have been an issue, no doubt.

Yes you are absolutely correct the bus line needs the correct netname at
the source and destination anywhere it is not connected on the same page. If
those connections were on the same page then the bus name can be left off
and the bus just used for a graphical object making those bussed connections
easier to follow across the page when viewed. This is because the individual
nets at each connection point to the bus will make the connections within
that page anyway. This occurs because the nets global option is only used to
connect like named nets across page boundaries. like named nets on any
individual page are connected always.

Going back to your earlier posting, your issue about connecting multiple
occurrences of like circuitry to differing nets in a complex hierarchy. In
your example you were talking about an A/D circuit connecting to different
bussed circuits in different occurrences. This won't work because all the
original circuits for the A/D are netnamed identically and you can't vary
the name for some occurrences without making a different root sheet with
those new netnames. One alternative would be to connect those varied nets to
individual wires where you needed to change the netname, then rename the
wire and join it to a newly named bus. This is messy and prone to errors,
Protel's ERC also doesn't handle connections with multiple netnames with any
grace and can let errors slip through. I cannot really recommend that you
try using this practice. It is easier to make a second root sheet of the
base circuitry by cut and pasting , reset the component designators and
change the key netnames for the new occurrence with new busnames. The minute
you want that route circuitry to connect to other nets or busses then you
are better off to make a new root sheet/page.

Good luck David, seems like you are on your way now. One recommendation
that I can make if you are continuing to use Protel, try signing up for the
Protel Users group forum at:
http://www.techservinc.com/protelusers/index.html
The group is made up of experienced Protel users worldwide. You can
usually get answers to your issues within hours, no matter what time of day
since there are usually Protel users around the world monitoring the posts
to that group in near real-time. I am a former member myself when I used
Protel day-day. It is a great bunch of guys on the forum listserver, you are
seldom left hanging or waiting for an answer (except when the listserver
goes down periodically).

--
Sincerely,
Brad Velander

"dave" <engineer_soul@yahoo.com> wrote in message
news:ab662096.0402041611.3dbf78b5@posting.google.com...

I appreciate the helpful comments. Thank you.

I know what the problem was, I'm just putting this here for the record
in case someone else has this problem.

I was 100% sure that the correct syntax for naming buses was with
parenthesis and colon, like BUS(0:11). Turns out that I needed to use
brackets and '..' instead, like BUS[0..11] . It still confuses me
because I have seen other designs using the parentheses syntax and
apparently they worked O.K. because boards have been correctly built
based on those projects before; however, those projects didn't use the
complex hierarchy model that I am using, that's the only thing I can
think of.

But anyway, that was the main problem. And furthermore, the bus has to
have a 'net label' at the source (from the component or part where it
is created), and a 'net label' at the destination (the bus going into
the pins for another component); it is not enough to have the port
connecting to the bus be named the same way (like D[0..X]). So, if the
bus entries are named D0,D1,D2; the bus label will be D[0..X]

For multisheet connectivity: buses connect to ports, the port does not
necessarily have to be named the same as the bus. When connecting
ports between sheet symbols in a parent sheet, if the bus symbol is
directly connecting the ports, it does not need a 'net label'; if it
is not directly connecting the ports, it needs the 'net label' at the
destination (the label being the same name as the source port) -- even
if the ports are named the same way because the scope of the 'complex
hierarchy' design does not take ports to be global.

Hope it helps someone avoid all the frustration and waste of time that
I experienced.

David