Protel 99SE "clearance constraint" in DRC

[learner]

Hi,
I auto routed my design and when I do a DRC, it say
Processing Rule : Clearance Constraint (Gap=8mil) (On the board ),(On
the board )
Violation between Pad 386EXTC-130(4878.303mil,9968.678mil) TopLayer
and
Pad 386EXTC-129(4897.988mil,9968.678mil)
TopLayer

How can I remove this error? It shows the same error for all the pads
of my processor. I made the footprint according to the package info.
Is it due to auto routing?
Any help is appreciated.
Thanks
Learner

 

[Roger Gt]

"learner" <sonalsingh28@yahoo.com> wrote in message
news:40cfbbf5.0407140048.474e9ed4@posting.google.com...
: Hi,
: I auto routed my design and when I do a DRC, it say
: Processing Rule : Clearance Constraint (Gap=8mil) (On the
board ),(On
: the board )
: Violation between Pad 386EXTC-130(4878.303mil,9968.678mil)
TopLayer
: and
: Pad 386EXTC-129(4897.988mil,9968.678mil)
: TopLayer
:
: How can I remove this error? It shows the same error for all the
pads
: of my processor. I made the footprint according to the package
info.
: Is it due to auto routing?
: Any help is appreciated.
: Thanks
: Learner

Measure the Foot print! If the space between the pads is less
than the "Clearance Constraint" the error is valid, which means
you need to:

1: redraw the foot print with wider spaces (not very practical)

2: Set the clearance constraint to slightly less than the
separation between the pads. For example IF the space between the
pads is 5 mil, set Clearance Constraint to 4.8 mil so the board
will give a clean DRC.

You may change the Constraint as a last test, leave it the at 8
mil for routing.

 

[Brad Velander]

Learner,
Alternatively you can devise a special rule to handle this
instance.

It is not uncommon for some SMT fine pitch parts today to
violate 8 mil DRC spacing. I have several times had to use 7.X
mil spacing on particular part's pads.

I note that there is slightly less than 20mils (19.685mils)
spacing between your pads. Subtract one pad width from that
figure and you will have the minimum spacing between pads.
(Assuming the two pads are equal sizes.)

Here is how I would do it.

A) Set up a Pad Class for your U??? Components pads, include all
of it's pads.
B) In DRC set a new rule using for Scope A the Pad Class that you
just created.
C) For scope B, set the same pad Class.
D) For your minimum clearance set a suitable spacing.
E) Make sure that it is set for "Different Nets Only".
F) Give your new Rule a name, Click OKAY.

--
Sincerely,
Brad Velander

"Roger Gt" <not@here.net> wrote in message
news:AndJc.20290$8m7.4190@newssvr27.news.prodigy.com...

"learner" <sonalsingh28@yahoo.com> wrote in message
news:40cfbbf5.0407140048.474e9ed4@posting.google.com...
: Hi,
: I auto routed my design and when I do a DRC, it say
: Processing Rule : Clearance Constraint (Gap=8mil) (On the
board ),(On
: the board )
: Violation between Pad 386EXTC-130(4878.303mil,9968.678mil)
TopLayer
: and
: Pad 386EXTC-129(4897.988mil,9968.678mil)
: TopLayer
:
: How can I remove this error? It shows the same error for all
the
pads
: of my processor. I made the footprint according to the
package
info.
: Is it due to auto routing?
: Any help is appreciated.
: Thanks
: Learner

Measure the Foot print! If the space between the pads is less
than the "Clearance Constraint" the error is valid, which means
you need to:

1: redraw the foot print with wider spaces (not very practical)

2: Set the clearance constraint to slightly less than the
separation between the pads. For example IF the space between
the
pads is 5 mil, set Clearance Constraint to 4.8 mil so the
board
will give a clean DRC.

You may change the Constraint as a last test, leave it the at 8
mil for routing.