D
dmitriym
Guest
Hello All!
I'm sorry, if my request is a little bit weird: I'm looking for some
verilog design with COMMON DESIGNER ERRORS (that are detectable by
modern LINTing tools). Actually, I'm doing research in this field, and
my target is to collect interesting errors in some kind of guide or
demo-project.
Maybe, someone from experiensed designers has been confronted with such
problem - I will be very much apperciated for any help!
I'm sorry, if my request is a little bit weird: I'm looking for some
verilog design with COMMON DESIGNER ERRORS (that are detectable by
modern LINTing tools). Actually, I'm doing research in this field, and
my target is to collect interesting errors in some kind of guide or
demo-project.
Maybe, someone from experiensed designers has been confronted with such
problem - I will be very much apperciated for any help!