programming question

[Clemens Ragger]

Hello

Assume the following easy example:

I have got an input signal which is 12 bits long.
Now I want that the output signal only contains the even bits

So I could write it this way:

outp(0) <= inp(0)
outp(1) <= inp(2)
outp(2) <= inp(4)

or also this way

for I 1 to 6 do
outp_h <= inp(2*I);
end loop
outp <= outp_h

is it correct that when I synthese both of this constructs the size is the
same? the outp_h is just seen a name for a 6 bit wire, its not a register
and cant store any value.

I hope you understand my problem

Cheers

 

[Jezwold]

I would use some thing like :

for i in 0 to 5 loop
outp(i)<=inp(2*i);
end loop;

which seems to make more sense.

 

[Clemens Ragger]

Yes of course, but I dont wanna use this implementation

I just wonder if my two "implementations" are indentical when I synthesize
it. Or is the second one bigger?

 

[Tim Hubberstey]

Clemens Ragger wrote:

Yes of course, but I dont wanna use this implementation

I just wonder if my two "implementations" are indentical when I synthesize
it. Or is the second one bigger?

They both describe identical hardware so there is no reason that there
_should_ be any difference. However, synthesizers are not perfect so the
only way to know for sure is to try it both ways and compare the
results. Write a short test module in each form and try it. I regularly
do this whenever I try out a new synthesizer or a new algorithm.

From a maintainability perspective, the loop is much clearer and less
prone to errors so I would most likely do it that way, even if there
were to be a slight size penalty.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com