programmable FIR and simulation

[PawelT]

Hello,
I tried to simulate example of generic FIR filter on page 82 from
book Uwe Meyer "Digital Signal Processing with FPGAs".
In book in simulation the first valid output is after 475 ns and zeros
before that.
I tried this example with MAxplus2 Baseline v10.2 and with new
ACF-file. Does anybody compile this?
After compilation and simulation on outputs Y_OUT there is appeared
unexpected new value dec*2046* after 125ns till 325ns,
and after 475 ns there is "correct" value from book.
And my question is: why this *unexpected* value (2046) appeared ?
I tried change options with original ACF-file and *this* value
appeared after changing Assign->Global Project Logic
Synthesis...->Optimize=10 (speed) to Optimize=5 (default value).
After that I tried change number of pipeline stages in lpm_mult, and
this *unexpected* value disappeared when constant Mpipe=1. For
Mpipe=2,3,4 there is bad value....
Any suggestions?
I tried this also with Quartus Web Edition 3.0 and simulation
generates bad Y_OUT....
Regards,
PawelT.

Pozdrawiam,
PawelT

 

[PawelT]

Hello again,
Does anybody know may I include here this example from book (vhdl
source)? I think about copyrights and so on.


Pozdrawiam,
PawelT

 

[MM]

After compilation and simulation on outputs Y_OUT there is appeared
unexpected new value dec*2046* after 125ns till 325ns,
and after 475 ns there is "correct" value from book.
And my question is: why this *unexpected* value (2046) appeared ?

There might be a difference in initial conditions... The question is whether
it really matters as soon as you get correct output when the data is
supposed to be valid. Is there some kind of flag signal saying when the
output data is valid?

/Mikhail

 

[Jim Lewis]

PawelT,
Note, I am not a lawyer, but
I believe fair use of a copyright allows one to quote
a short section of copyrighted sources for the purposes
of discussion. You could always ask the author. Go to
goggle and do a search through the newsgroups.

Cheers,
Jim

PawelT wrote:

Hello again,
Does anybody know may I include here this example from book (vhdl
source)? I think about copyrights and so on.


Pozdrawiam,
PawelT

 

[PawelT]

For discussion I include the code of fir example.


-- This is a generic FIR filter generator
-- It uses W1 signed bit data/coefficients bits
LIBRARY lpm; -- Using predefined packages
USE lpm.lpm_components.ALL;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY fir_prog IS ------> Interface
GENERIC (W1 : integer := 9; -- Input bit width
W2 : integer := 18;-- Multiplier bit width 2*W1
W3 : integer := 19;-- Adder width = W2+log2(L)-1
W4 : integer := 11;-- Output bit width
L : integer := 4; -- Filter length
-- for Mpipe = 1 output Y_OUT is OK (PT)
Mpipe : integer := 3-- Pipeline steps of multiplier
);
PORT ( clk : IN STD_LOGIC;
Load_x : IN STD_LOGIC;
x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
-- c_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); -- (PT)
y_out : OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0));
END fir_prog;

ARCHITECTURE arch_fir OF fir_prog IS

SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
SUBTYPE N3BIT IS STD_LOGIC_VECTOR(W3-1 DOWNTO 0);
TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT;
TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT;
TYPE ARRAY_N3BIT IS ARRAY (0 TO L-1) OF N3BIT;

SIGNAL x : N1BIT;
SIGNAL y : N3BIT;
SIGNAL c : ARRAY_N1BIT; -- Coefficient array
SIGNAL p : ARRAY_N2BIT; -- Product array
SIGNAL a : ARRAY_N3BIT; -- Adder array

BEGIN

Load: PROCESS ------> Load data or coefficient
BEGIN
WAIT UNTIL clk = '1';
IF (Load_x = '0') THEN
-- load coefs from X_IN input (PT)
c(L-1) <= x_in; -- Store coefficient in register
FOR I IN L-2 DOWNTO 0 LOOP -- Coefficients shift one
c(I) <= c(I+1);
END LOOP;
ELSE
x <= x_in; -- Get one data sample at a time

END IF;
END PROCESS Load;


SOP: PROCESS (clk, load_x) ------> Compute sum-of-products
BEGIN
IF clk'event and (clk = '1') THEN
FOR I IN 0 TO L-2 LOOP -- Compute the transposed
a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); -- filter adds
END LOOP;
a(L-1) <= p(L-1)(W2-1) & p(L-1); -- First TAP has
END IF; -- only a register
y <= a(0);
END PROCESS SOP;

-- Instantiate L pipelined multiplier
MulGen: FOR I IN 0 TO L-1 GENERATE
Muls: lpm_mult -- Multiply p(i) = c(i) * x;
GENERIC MAP ( LPM_WIDTHA => W1, LPM_WIDTHB => W1,
LPM_PIPELINE => Mpipe,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTHP => W2,
LPM_WIDTHS => W2)
PORT MAP ( clock => clk, dataa => x,
-- this line to turn-off pipelining (PT)
-- PORT MAP ( dataa => x,
datab => c(I), result => p(I));
END GENERATE;
y_out <= y(W3-1 DOWNTO W3-W4);
END arch_fir;


Pozdrawiam,
PawelT