Programmable Counter

Hi,
There is an up down counter which has a programmable upper limit
and lower limit, which can be programmed when enable is low. Counter
starts counting when enable is high . Now if one signal mode will
decide whether it is up or down , then how am i suppose to capture the
upper limit and lower limit ?

 

On Aug 13, 10:30 pm, gtalk.nik...@gmail.com wrote:

Hi,
   There is an up down counter which has a programmable upper limit
and lower limit, which can be programmed when enable is low. Counter
starts counting when enable is high . Now if one signal mode will
decide whether it is up or down , then how am i suppose to capture the
upper limit and lower limit ?

Also the counter is wrap around.. next time when enable goes low again
the user has ability to reconfigure the limits or stay with old ones

 

[gabor]

On Aug 13, 1:33 pm, gtalk.nik...@gmail.com wrote:

On Aug 13, 10:30 pm, gtalk.nik...@gmail.com wrote:

Hi,
There is an up down counter which has a programmable upper limit
and lower limit, which can be programmed when enable is low. Counter
starts counting when enable is high . Now if one signal mode will
decide whether it is up or down , then how am i suppose to capture the
upper limit and lower limit ?

Also the counter is wrap around.. next time when enable goes low again
the user has ability to reconfigure the limits or stay with old ones

I'm confused. Are you saying you want to "capture" the upper or lower
limit from the current counter value? Or you have a separate upper or
lower limit input to your module that you need to sample only when the
count enable is low? Either way you would need a register for each
limit which is only enabled at the appropriate time when not counting.

Maybe if you can more concisely say what you're trying to do, you
will figure out how to do it.

Regards,
Gabor

 

On Aug 13, 11:59 pm, gabor <ga...@alacron.com> wrote:

On Aug 13, 1:33 pm, gtalk.nik...@gmail.com wrote:

On Aug 13, 10:30 pm, gtalk.nik...@gmail.com wrote:

Hi,
   There is an up down counter which has a programmable upper limit
and lower limit, which can be programmed when enable is low. Counter
starts counting when enable is high . Now if one signal mode will
decide whether it is up or down , then how am i suppose to capture the
upper limit and lower limit ?

Also the counter is wrap around.. next time when enable goes low again
the user has ability to reconfigure the limits or stay with old ones

I'm confused.  Are you saying you want to "capture" the upper or lower
limit from the current counter value?  Or you have a separate upper or
lower limit input to your module that you need to sample only when the
count enable is low?  Either way you would need a register for each
limit which is only enabled at the appropriate time when not counting.

Maybe if you can more concisely say what you're trying to do, you
will figure out how to do it.

Regards,
Gabor

Hi,
Yes there is a seperate upper and lower limit for the counter, but
that could be taken from one
input when enable is low for two clock cycles. In first cycle upper
limit can be given and other cycle lower limit can be given and these
values should be stored in two seperate registers.

Now when enable is asserted counter should start counting from the
limit which user says i.e up/down depending on the up/down signal. But
here the problem is how to transfer the limits to a temporary register
which should be incremented/decremented depending on up/down signal.

Moreover, if enable goes low again inbetween the up down operation,
the user can reconfigure the limits or stay with the old one's, so i
need to retain those previous values (which is not of a problem).

I hope i am able to convey it properly now.

Thanks

 

[glen herrmannsfeldt]

gtalk.nikhil@gmail.com wrote:
(snip)

Yes there is a seperate upper and lower limit for the counter, but
that could be taken from one
input when enable is low for two clock cycles. In first cycle upper
limit can be given and other cycle lower limit can be given and these
values should be stored in two seperate registers.

A synchronous up counter is a register and an adder
(to add one). A synchronous up-down counter is a
register and add/subtract to add or subtract one.

If you want different upper/lower limits, you test
for the lower/upper value and, through a multiplexer,
feed the upper/lower value in instead of the next
count. (Also test the up/down line.)

In most cases the register will be clocked with a clock
enable, which is actually a multiplexer in front of
clocked flip-flops. You might save a little with one
big multiplexer for clock not enabled, up, down, upper,
or lower limit. Well, that is five choices, but it still
probably works fine.

-- glen