Programmable clock, FPGA PLLs, and Actel PLL Core

[dave]

Escenario : Need a clock system with range from ~50Mhz to 150Mhz with
as much granularity as possible to drive an FPGA.


Could anyone please suggest options on how to better implement this
clock system.? I've looked at programmable clocks from Cypress,
Maxim-ic, but these require some I2C or 2-wire interface, and I don't
have a microcontroller on board, just the FPGA so I'd need to put a
I2C core... . I've looked at using the PLL core in the FPGA (Actel in
this case), but I find the documentation about it to be extremely poor
as to how to really implement it.

By the way, if anybody has had experience using the PLL core in Actel,
could you please give a simple example on how to use the core
generated by "Actgen." I've read the document on "PLL dynamic
reconfiguration using JTAG," and I still don't understand
completely....

Thanks in advance,

David

 

[Jay]

Peter,

In article <402BBFA1.49FA2DB5@xilinx.com>

You need to be more specific about granularity, jitter, and your budget.
Here is one extreme:
I am just finishing a project where we combine a small Spartan3 plus an
ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz (all
the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
uses some unconventional tricks...

Any plans to make an application note describing your setup? It sounds
like a very cool design.

Are you doing something like frequency division in the FPGA with
counters and multiplication with the PLL? Perhaps using different clocks
& divider combos to cover the range??

Thanks,
Jay.

 

[Peter Alfke]

You need to be more specific about granularity, jitter, and your budget.
Here is one extreme:
I am just finishing a project where we combine a small Spartan3 plus an
ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz (all
the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
uses some unconventional tricks...

DDS is the traditional method to achieve finest granularity, but it
creates lots of jitter, and is non-trivial at 150 MHz.

Peter Alfke
===================================
dave wrote:

Escenario : Need a clock system with range from ~50Mhz to 150Mhz with
as much granularity as possible to drive an FPGA.

Could anyone please suggest options on how to better implement this
clock system.? I've looked at programmable clocks from Cypress,
Maxim-ic, but these require some I2C or 2-wire interface, and I don't
have a microcontroller on board, just the FPGA so I'd need to put a
I2C core... . I've looked at using the PLL core in the FPGA (Actel in
this case), but I find the documentation about it to be extremely poor
as to how to really implement it.

By the way, if anybody has had experience using the PLL core in Actel,
could you please give a simple example on how to use the core
generated by "Actgen." I've read the document on "PLL dynamic
reconfiguration using JTAG," and I still don't understand
completely....

Thanks in advance,

David

 

[Peter Alfke]

Jay, give me a few weeks to publish.
In a nutshell: 10 MHz xtal osc gets multiplied to 80 MHz, drives Direct
Digital Synthesis accumulator, a "magic circuit" then multiplies the
frequency and reduces the jitter. The Spartan-3 output drives the ICS
PLL for further jitter reduction and multiplication by up to 8.
Nice GUI and display control by PicoBlaze.
Read about it in XCell, and I will also brag about characterization
results in this ng, once we are finished. Fun project

Peter Alfke
================================
Jay wrote:

Peter,

In article <402BBFA1.49FA2DB5@xilinx.com
You need to be more specific about granularity, jitter, and your budget.
Here is one extreme:
I am just finishing a project where we combine a small Spartan3 plus an
ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz (all
the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
uses some unconventional tricks...

Any plans to make an application note describing your setup? It sounds
like a very cool design.

Are you doing something like frequency division in the FPGA with
counters and multiplication with the PLL? Perhaps using different clocks
& divider combos to cover the range??

Thanks,
Jay.

 

[Jim Granville]

Peter Alfke wrote:

Jay, give me a few weeks to publish.
In a nutshell: 10 MHz xtal osc gets multiplied to 80 MHz, drives Direct
Digital Synthesis accumulator, a "magic circuit" then multiplies the
frequency and reduces the jitter. The Spartan-3 output drives the ICS
PLL for further jitter reduction and multiplication by up to 8.
Nice GUI and display control by PicoBlaze.
Read about it in XCell, and I will also brag about characterization
results in this ng, once we are finished. Fun project

Yes, sounds a great 'dynamic range' demonstration.
I've changed the topic heading if you want to keep us posted

Any plans to add a 640MHz reciprocal Frequency counter - or
do you have this included already, just to prove the Synth is
on the right frequency

-jg

 

[Peter Alfke]

Frequency counter is the next project. Since we have case, power supply,
display and all the mechanical trivia established, it is easy to build a
separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
Time base oscillator promises < 3 ppm (Maxim).
The "reciprocal" concept made it into a Xilinx "UltraController"
presentation and demo.
I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
I could use the newest Virtex-II ProX which is 3 times faster, but I do
not see so much demand for a 5 GHz input resolution (LVDS). Gettinga
bit esoteric, but the chip can do it...
Keep you posted.

Peter Alfke
==========================
Jim Granville wrote:

Yes, sounds a great 'dynamic range' demonstration.
I've changed the topic heading if you want to keep us posted

Any plans to add a 640MHz reciprocal Frequency counter - or
do you have this included already, just to prove the Synth is
on the right frequency

-jg

 

[Jim Granville]

Peter Alfke wrote:

Frequency counter is the next project. Since we have case, power supply,
display and all the mechanical trivia established, it is easy to build a
separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
Time base oscillator promises < 3 ppm (Maxim).
The "reciprocal" concept made it into a Xilinx "UltraController"
presentation and demo.
I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
I could use the newest Virtex-II ProX which is 3 times faster, but I do
not see so much demand for a 5 GHz input resolution (LVDS). Gettinga
bit esoteric, but the chip can do it...
Keep you posted.

Thanks,
Will this fit into your 'small spartan 3', alongside the Synth ?
Can you feed the 1.5GHz into a flip flop / ring counter reliably ?
What about Fmax of a variable modulus divider 1st stage ?
(was it the 11C90 (?) from fairchild ?)

-jg

 

[dave]

Thank you for your reply Mr. Alfke.

Your project does sound very interesting. I think that what I'm
looking for is way too much simpler than that. 1 Hz granularity would
be very nice, but I could work with 1Mhz steps ok. At this point I
really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+
range arround these frequencies would help me a lot too.

Ideally I could use the PLL core on the FPGA to input a fixed
frequency clock (150Mhz) and have it output the frequencies I need
(~60, ~100, ~150 MHz) -- one at a time, not all three at the same
time, I would select which one through internal logic or JTAG. This
ouput clock is the one driving my whole FPGA logic inside.

I've been having a hard time understanding the usage of the PLL
component in ACTEL and the documentation is not really helping me
much. So, I'm open to suggestions, while I keep trying to even get the
PLL core to synthezise.

I'll keep an eye on Xilinx's magazine for your published project
because it does sound interesting.


Thanks again,

David.

 

[Peter Alfke]

11C90, 10/11 ECL variable modulus prescaler, memories of the early
'seventies...It's amazing that we could build frequency synthesizers
running close to a GHz at that time. Lots of power though, and tricky
pc-board layout. Now it's so much more integrated, and one can easily
recover from design mistakes. I love FPGAs !

The trouble with a fast front-end in our FPGAs is that almost everything
has gotten much faster ( and more sophisticated ) in the past 5 years,
but the raw toggle frequency of a LUT+flip-flop has not doubled from the
400 MHz we could do 5years ago in XC4000XL. The flip-flop is much
faster, but the routing, although flexible, is less direct. That's why I
have given up doing it that way.

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.
And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

Anybody need a counter with resolution between 1.5 and 5 GHz ?
Peter Alfke
=================================
Jim Granville wrote:

Peter Alfke wrote:
Frequency counter is the next project. Since we have case, power supply,
display and all the mechanical trivia established, it is easy to build a
separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
Time base oscillator promises < 3 ppm (Maxim).
The "reciprocal" concept made it into a Xilinx "UltraController"
presentation and demo.
I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
I could use the newest Virtex-II ProX which is 3 times faster, but I do
not see so much demand for a 5 GHz input resolution (LVDS). Gettinga
bit esoteric, but the chip can do it...
Keep you posted.

Thanks,
Will this fit into your 'small spartan 3', alongside the Synth ?
Can you feed the 1.5GHz into a flip flop / ring counter reliably ?
What about Fmax of a variable modulus divider 1st stage ?
(was it the 11C90 (?) from fairchild ?)

-jg

 

[Peter Alfke]

Let me put in a plug for the Digital Clock Manager in Virtex-II.
It can take in any frequency between 1MHz and >300 MHz, and
simultaneously multiply and divide it by two numbers in the range of
1...32. (Output frequency must be >24 MHz, though).
You can do 200 MHz times 15, divided by 19 if you feel like it. The fact
that 200 MHz times 15 is very high does not matter, the DCM does the
mathematical manipulation without going to GHz...
So you can generate your frequencies from many different input sources,
but only one frequency per DCM. You can reprogram the DCM on the fly,
but it is somewhat complicated in today's circuits.
Peter Alfke
=================
dave wrote:

Thank you for your reply Mr. Alfke.

Your project does sound very interesting. I think that what I'm
looking for is way too much simpler than that. 1 Hz granularity would
be very nice, but I could work with 1Mhz steps ok. At this point I
really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+
range arround these frequencies would help me a lot too.

Ideally I could use the PLL core on the FPGA to input a fixed
frequency clock (150Mhz) and have it output the frequencies I need
(~60, ~100, ~150 MHz) -- one at a time, not all three at the same
time, I would select which one through internal logic or JTAG. This
ouput clock is the one driving my whole FPGA logic inside.

I've been having a hard time understanding the usage of the PLL
component in ACTEL and the documentation is not really helping me
much. So, I'm open to suggestions, while I keep trying to even get the
PLL core to synthezise.

I'll keep an eye on Xilinx's magazine for your published project
because it does sound interesting.

Thanks again,

David.

 

[Jim Granville]

Peter Alfke wrote:
<snip>

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.

What does a Spartan 3 allow ?

And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

How do you use a Ser.Des as a freq divider/counter ?

Anybody need a counter with resolution between 1.5 and 5 GHz ?

Just to give you a target, to fully challenge the grey matter,
this company offers 10 digits/second ($2K), and 12 digits/second
models($3K).

http://we.home.agilent.com/cgi-bin/bvpub/agilent/Product/cp_Product.jsp?NAV_ID=-11154.0.00&LANGUAGE_CODE=eng&COUNTRY_CODE=ZZ

8 digits / second is realively easy, but 10/12 are much more
challenging...

-jg

 

[Austin Lesea]

Jim,

The DCM has a divide by two input prescalar. I was able to get the
clock in to the prescalar at 1.15 GHz, which then gets divided by two
quite nicely. This was LVDS input, with everything just right to drive
the input (as reflections, matching, etc. becomes really tricky at GHz
speeds, so simulations and matching stubs and tricks becomes necessary,
but a Mini-Circuits -> 6 GHz amplifier is about $1.50, so the front end
is challenging, but not expensive). Need a differential balun, etc.

Looks more like a microwave LNA than a clock input to an FPGA.....the
same techniqies would get applied to drive a 2vp2 MGT receiver as well,
but the SI is a lot easier, as the MGT is designed for 3.125 Mb/s rates,
wheras the clock inputs are not designed for GHz frequencies (because
the clock trees don't work there).

Peter's comment about 4K is true: a hand placed route from an input pin
to the nearest CLB FF can toggle (divide by two) up to about 1 Ghz in
Virtex II, or II Pro, or S3. It is just tricky because you have to find
the shortest and best path.

How many people need GHz divide by capability? Would it be nice to have
a 10GHz prescalar built into some pins? What would you use it for? I
am afraid it would be too much trouble for too little business.

Austin



Jim Granville wrote:

Peter Alfke wrote:
snip


The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.


What does a Spartan 3 allow ?

And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not
difficult.


How do you use a Ser.Des as a freq divider/counter ?


Anybody need a counter with resolution between 1.5 and 5 GHz ?


Just to give you a target, to fully challenge the grey matter,
this company offers 10 digits/second ($2K), and 12 digits/second
models($3K).

http://we.home.agilent.com/cgi-bin/bvpub/agilent/Product/cp_Product.jsp?NAV_ID=-11154.0.00&LANGUAGE_CODE=eng&COUNTRY_CODE=ZZ


8 digits / second is realively easy, but 10/12 are much more
challenging...

-jg

 

[Peter Alfke]

Jim Granville wrote:

Peter Alfke wrote:
snip

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.

What does a Spartan 3 allow ?
Nothing, no MGTs. Flip-flops counting perhaps at 500 MH ( with care,

remember Spartan emphasizes low cost, not high speed).

And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

How do you use a Ser.Des as a freq divider/counter ?
Just as a oversampled input, generating a parallel 10 or 20 bit word,

then processing this as data ( accumulator, etc)

Anybody need a counter with resolution between 1.5 and 5 GHz ?

Just to give you a target, to fully challenge the grey matter,
this company offers 10 digits/second ($2K), and 12 digits/second
models($3K).
Well, I will use internal "time base" of 100 MHz for 1 sec = 8 digits.

When the input signal is >100 MHz, the resolution goes up, of course.
My time base is "only" 3 ppm worst case, but the Maxim oscillator can be trimmed.
I have no intentions of driving Agilent out of business. They have a 65
year head start...
Peter Alfke
>

 

[Jim Granville]

Austin Lesea wrote:

Jim,

The DCM has a divide by two input prescalar. I was able to get the
clock in to the prescalar at 1.15 GHz, which then gets divided by two
quite nicely.
snip

Peter's comment about 4K is true: a hand placed route from an input pin
to the nearest CLB FF can toggle (divide by two) up to about 1 Ghz in
Virtex II, or II Pro, or S3. It is just tricky because you have to find
the shortest and best path.

How many people need GHz divide by capability?

Frequency synthesisers would be one, and precise time/phase measurements
could be another. Precise time is a little more difficult, as you
need to capture, but this would, of course, clock on both edges

Would it be nice to have a 10GHz prescalar built into some pins?

Yes. Would not need to be many.

What would you use it for?

See above.

I am afraid it would be too much trouble for too little business.

Possibly, but consider that the resolution of a FPGA in terms of
jitter, and Register Apertures are in the some picosecond region, but
that currently to get a frequecy above ~500MHz (2000ps) into the fpga
needs special care..
That would indicate a dedicated Ctr/Capture block, like the MGTs.

-jg

 

[Jim Granville]

Peter Alfke wrote:

Just to give you a target, to fully challenge the grey matter,
this company offers 10 digits/second ($2K), and 12 digits/second
models($3K).

Well, I will use internal "time base" of 100 MHz for 1 sec = 8 digits.
When the input signal is >100 MHz, the resolution goes up, of course.
My time base is "only" 3 ppm worst case, but the Maxim oscillator can be trimmed.
I have no intentions of driving Agilent out of business. They have a 65
year head start...

here's another one :
http://www.coherent.com.au/physical/prod_instrum_time.htm
Uses a 10GHz VCO, and gives 11 digits/second.
this claims 25ps single shot time interval resolve, rather ahead of
Agilent's 500ps or 150ps.
with some smart thinking, 25ps should be close to a Spartan 3?

-jg

 

[Jean Nicolle]

he, I may have a solution
http://www.fpga4fun.com/shop_I2CPLL.html

Did this project just a few weeks back...
Jean

 

[Thomas Heller]

Peter Alfke <peter@xilinx.com> writes:

11C90, 10/11 ECL variable modulus prescaler, memories of the early
'seventies...It's amazing that we could build frequency synthesizers
running close to a GHz at that time. Lots of power though, and tricky
pc-board layout. Now it's so much more integrated, and one can easily
recover from design mistakes. I love FPGAs !

The trouble with a fast front-end in our FPGAs is that almost everything
has gotten much faster ( and more sophisticated ) in the past 5 years,
but the raw toggle frequency of a LUT+flip-flop has not doubled from the
400 MHz we could do 5years ago in XC4000XL. The flip-flop is much
faster, but the routing, although flexible, is less direct. That's why I
have given up doing it that way.

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.
And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

Anybody need a counter with resolution between 1.5 and 5 GHz ?

Not a counter, but I need to generate edges with subnanosecond
timeresolution, and also measure the precise position of edges with the
same resolution.

Regards,

Thomas Heller

 

[Kolja Sulimma]

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.
And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

Anybody need a counter with resolution between 1.5 and 5 GHz ?

YES!

I really would like to use a fast Deserializer (preferably 10GHz)
without clock and data recovy. Just give me sample data from the input
pins in raw form in a slower parallel format.
The sample frequeny should be a multiple of the local reference clock
and the phase should not be pulled by input transitions.

My information from about a year ago is that the Virtex-II-Pro SERDES
could not be operated in a dumb mode like that. In principle this
should be simpler than the usual operating mode. The question is only
if there is a way to turn of all the unwanted functionality.

If you have found a way to do that, please tell me.

Kolja Sulimma

 

[Marius Vollmer]

Jim Granville <no.spam@designtools.co.nz> writes:

Just to give you a target, to fully challenge the grey matter,
this company offers 10 digits/second ($2K), and 12 digits/second
models($3K).

Could you explain what "10 digits/second" means? I have no idea...
Thanks!

 

[dave]

Well ! this is great. Almost exactly what I want, just that I want it
to put it my own board (I'm designing my PCB still).

I think I'm getting closer to be able to use the PLL core in the FPGA,
which is my ideal solution. But I'll keep in mind your system.


On a separate note, could someone please suggest a good and fast news
server (public preferably) where to read/post to this newsgroup? I'm
just using Google's web interface and it takes almost 3 hrs. for my
own post to show up, and by then I notice some of you guys have
already several replies to the post that I can't see yet. (I see the
replies in news-reader.org but I can't post there)


Thanks.

David


"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:<Pr_Wb.24547$Tu6.22239@newssvr25.news.prodigy.com>...

he, I may have a solution
http://www.fpga4fun.com/shop_I2CPLL.html

Did this project just a few weeks back...
Jean