As you suggest, a SystemVerilog module can have a port of
interface type. When you instantiate such a module, you
then hook its interface-type port to an instance of a
suitable interface, or perhaps to a modport in such an
interface instance.
You cannot do the same thing with programs or modules,
but only with interfaces.
Packages are somewhat different. Generally you would
import a package into a module. In that way, definitions
in the package become visible to the module. There is
no way to pass a pcakage through a module's port, and
I cannot see how that would make any sense.
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