product of real and (integer)(after converted to real one) v

[senthil]

hello friends

i found one fatal error , when i multiply two signals ie.,

one signal is being real type and another one is integer type.. coding below

entity < >
port ( w : in real;n : integer; result : out real);
end < >
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w
i found on the screen

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9
ie., at result <= n * tmp;
please give some ideas...
thank u expect some suggestions

 

[Jonathan Bromley]

"senthil" <bhuvasen@hotmail.com> wrote in message
news:3045a319.0401210514.583b98ae@posting.google.com...

entity
port ( w : in real;n : integer; result : out real);
end
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9

Which simulator?

Don't forget that n will initially be -MAXINT, and even
if you force a value on to n, the multiply will take
place with the old value until one delta cycle later
when the new value on n has propagated through the
assignment to tmp.

Interesting... what are you doing with real ports?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[senthil]

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bulv1h$dlq$1$8302bc10@news.demon.co.uk>...

"senthil" <bhuvasen@hotmail.com> wrote in message
news:3045a319.0401210514.583b98ae@posting.google.com...

entity
port ( w : in real;n : integer; result : out real);
end
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9

Which simulator?

Don't forget that n will initially be -MAXINT, and even
if you force a value on to n, the multiply will take
place with the old value until one delta cycle later
when the new value on n has propagated through the
assignment to tmp.

Interesting... what are you doing with real ports?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

suppose if i declared the n as variable inside the process and goes
frm 0 to 10 means. for that i put one for loop with that inside i put
tmp <= real;
result <= w * tmp;
is it possible to do like that? and here i use modelsim simulator 5.5
it also keep interesting , and it will use in my ifft module..
and pls mention what are all the other faq website related to vhdl...
expecting ur reply eagerly

 

[senthil]

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bulv1h$dlq$1$8302bc10@news.demon.co.uk>...

"senthil" <bhuvasen@hotmail.com> wrote in message
news:3045a319.0401210514.583b98ae@posting.google.com...

entity
port ( w : in real;n : integer; result : out real);
end
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9

Which simulator?

Don't forget that n will initially be -MAXINT, and even
if you force a value on to n, the multiply will take
place with the old value until one delta cycle later
when the new value on n has propagated through the
assignment to tmp.

Interesting... what are you doing with real ports?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

suppose if i declared the n as variable inside the process and goes
frm 0 to 10 means. for that i put one for loop with that inside i put
tmp <= real;
result <= w * tmp;
is it possible to do like that? and here i use modelsim simulator 5.5
it also keep interesting , and it will use in my ifft module..
and pls mention what are all the other faq website related to vhdl...
expecting ur reply eagerly

 

[Eyck Jentzsch]

senthil wrote:

hello friends

i found one fatal error , when i multiply two signals ie.,

one signal is being real type and another one is integer type.. coding below

entity
port ( w : in real;n : integer; result : out real);
end
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w
i found on the screen

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9
ie., at result <= n * tmp;
please give some ideas...
thank u expect some suggestions
The problem here is that tmp will initially hold -1e+308. So in the

first delta cycle you will get a multiplication of -1e+308 * -1e+308
which causes the overflow. Consider using a process or do the conversion
in one line:

result <= w*real;

or:

mult: process(n, w)
variable tmp: real;
begin
tmp:=real;
result<=w*tmp;
end mult;

HTH

-Eyck

 

[senthil]

Eyck Jentzsch <jentzsch@cadence.com> wrote in message news:<400f6c2c@news.cadence.com>...

senthil wrote:
hello friends

i found one fatal error , when i multiply two signals ie.,

one signal is being real type and another one is integer type.. coding below

entity
port ( w : in real;n : integer; result : out real);
end
architecture < > of < > is
signal tmp : real;
begin
tmp <= real;
result <= w*tmp;
end <>;

after i force values to w
i found on the screen

Fatal: Value -Inf is out of range -1e+308 to 1e+308
Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9
ie., at result <= n * tmp;
please give some ideas...
thank u expect some suggestions
The problem here is that tmp will initially hold -1e+308. So in the
first delta cycle you will get a multiplication of -1e+308 * -1e+308
which causes the overflow. Consider using a process or do the conversion
in one line:

result <= w*real;

or:

mult: process(n, w)
variable tmp: real;
begin
tmp:=real;
result<=w*tmp;
end mult;

HTH

-Eyck

hello eyck,
i do in ur way i got ur answer. and i have doubt on this ,, ie., can i
use this type of technique to direct implementation of the dft or
idft? ie.,
in theformula x = 1/N E x(k)e(j2pink/N); i have the x(k) store in
Array. and for N= 8point means , i declared one signal => Wn =2pi/N;
and for clk'event n varies from 0 to 7 inside that the k varies form 0
to 7 for each n values.
for this one , can i implement that ur given above techniques? with
the values of Wn , i product this with ie., Wn*n <= Wk some signal and
inside the for loop of k values Wk*k <= some signal .. finally i found
that , the k values for corresponding intermediate values ie.,
e(j2pink/N) are differ by one clk period. ie., after the k = 6,
intermediate value will give the value when k = 6.

what the problem behind that.. pls giv some suggestion to do the ifft
or fft in another way.. expecting ur reply eagerly..
thank u.