Processor Debug interface

[designer]

Hi all,
I wanted to know about the different debug interfaces used(or
standards present like JTAG etc...) in a wireless SOC having a RISC
processor. ARM uses some thing called trace debugging, I didn't get
the concept clearly. Can anyone enlighten me on the same. I know about
JTAG.
Thanks,
Vittal

 

[Marcus Harnisch]

Vittal, this is hopelessly off-topic here.

designer <vittal.patil@gmail.com> writes:

I wanted to know about the different debug interfaces used(or
standards present like JTAG etc...) in a wireless SOC having a RISC
processor. ARM uses some thing called trace debugging, I didn't get
the concept clearly. Can anyone enlighten me on the same. I know about

"Tracing" (aka non-invasive debug) is the term used for gathering data
about the execution history of a processor. From this information, the
trace unit (e.g. ARM Embedded Trace Macrocell, ETM) generates a packed
data stream and dumps it via a high-speed interface.

Debug software can analyze collected trace data and e.g. visualize the
code paths executed by the processor. Trace is also useful for
profiling code.

For everything else move to other groups, e.g. comp.sys.arm

Regards
Marcus

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