Process Statements in VHDL

[samsky electronique]

Hi I have a question

Here is an example

process(sig1,sig2,A,B,C)
begin
if (A > "001" and B > "010") then
sig1 <= '1';
else
sig1 <= '0';
end if;

if (C > "011" and sig1 = '0') then
sig2 <= '1';
else
sig2 <= '0';
end if;

end process;

It this advisable to write code like this, or should sig1 be in a
different process. What generally happens when a signal is assigned to
and also read to in the same process. What would happen if i have the
sig1 if-then-else statement, below the sig2 if-then-else statement, how
would the simulator behave ?

appreciate all the detail that I can get.