process factorisation

[titi]

Is it better to write p1 and p2, or to write p_1_and_2?
Will p1 and p2, or p_1_and_2 have the same behaviour/be equally
synthetisable?


inputs:
clock, something,Reset, some_condition : std_logic ;
outputs:
s1 : std_logic ;


signal clock2 : std_logic ;
signal Not_clock : std_logic ;
signal over : std_logic ;

clock2 <= clock;
Not_clock <= not clock;

p_1rocess(Reset,clock2,something, over)
begin
if Reset ='1' then
s1 <= '0';
elsif (something ='1') then
if clock2'event and clock2 ='0' then
s1 <= '1';
end if;
elsif over ='1' then
s1 <= '0';
end if;
end process;


p_2rocess(Not_clock,some_condition)
begin
if Not_clock'event and Not_clock ='1' then
if(some_condition) then
over <= '0';
else
over <= '1';
end if;
end if;
end process;




p_1_and_2rocess(clock,some_condition)
begin
if Reset ='1' then
s1 <= '0';
elsif falling_edge(clock) then
if(some_condition) then
over <= '0';
else
over <= '1';
end if;
if (something ='1') then
s1 <= '1';
end if;
elsif over ='1' and (something /= '1') then
s1 <= '0';
end if;
end process;

 

[Ralf Hildebrandt]

titi schrieb:

Is it better to write p1 and p2, or to write p_1_and_2?
Will p1 and p2, or p_1_and_2 have the same behaviour/be equally
synthetisable?

Simulation is the key to verify if two solutions have the same behavior.

p_1rocess(Reset,clock2,something, over)
begin
if Reset ='1' then
s1 <= '0';
elsif (something ='1') then
if clock2'event and clock2 ='0' then
s1 <= '1';
end if;
elsif over ='1' then
s1 <= '0';
end if;
end process;

This is not synthesizable, as you could have verified it for yourself.
Use the template for flipflops:

process(reset,clk)
begin
if (reset='0') then
-- do some reset
elsif falling_edge(clk) then
-- do some synchronous stuff
end if;
end process;

Don't use any else / elsif branches behind a branch with an 'event
attribute (no elsif over='1' then)!
Don't enable / disable branches with an 'event attribute moving them
into a deeper hierarchy of else-branches (no 'event inside the elsif
something='1' then branch)! If you need clock-gating, then you have to
build some extra clock-gating logic (a latch and a gate).

p_2rocess(Not_clock,some_condition)
begin
if Not_clock'event and Not_clock ='1' then
if(some_condition) then
over <= '0';
else
over <= '1';
end if;
end if;
end process;

This process is almost ok. A synchronous flipflop. You don't need
some_condition in the sensitivity list.
Have in mind, that you only have the synchronous reset for signal "over".


Ralf