process and signal (urgent)

A

Amit

Guest
Hi group,

I need to combine two entities. One is a debouncer and the other is a
counter. What I have in hand is two entities in two projects.

entity debuncer is

port(
clk, key: in std_logic;
z: out std_logic;
q: buffer std_logic_vector(9 downto 0));

end debouncer;


I need to connect the z output to a counter so I have created a
process as:

mycounter: process(????)

what I'm confused about is that I don't know if I have to consider
"clk" or "z" in sensitivity list or what? I have never used process so
far and all examples in books are only about one entity and one
process in them.

any suggestions will be apprecaited greatly.


thanks,
ak
 
On Oct 6, 8:20 pm, Amit <amit.ko...@gmail.com> wrote:
Hi group,

I need to combine two entities. One is a debouncer and the other is a
counter. What I have in hand is two entities in two projects.

entity debuncer is

port(
clk, key: in std_logic;
z: out std_logic;
q: buffer std_logic_vector(9 downto 0));

end debouncer;

I need to connect the z output to a counter so I have created a
process as:

mycounter: process(????)

what I'm confused about is that I don't know if I have to consider
"clk" or "z" in sensitivity list or what? I have never used process so
far and all examples in books are only about one entity and one
process in them.

any suggestions will be apprecaited greatly.

thanks,
ak
Click to expand...

First of all you can't connect two ports from different entities in
deiffernet PROJECTs! both must be in the same project. Then, you can
have two entities or most simpler one entity and one process in it
containing both debouncer and counter. why don't you creat your
counter in the debouncer entity?!
is it the z signal you're trying to count? then can creat your process
with 'clk' in the sensitivity list, and use 'z' as a clock enable
signal like the below structure:

mycounter:
process(clk)
begin
if rising_edge(clk) then

end if;
 
On Oct 6, 8:20 pm, Amit <amit.ko...@gmail.com> wrote:
Hi group,

I need to combine two entities. One is a debouncer and the other is a
counter. What I have in hand is two entities in two projects.

entity debuncer is

port(
clk, key: in std_logic;
z: out std_logic;
q: buffer std_logic_vector(9 downto 0));

end debouncer;

I need to connect the z output to a counter so I have created a
process as:

mycounter: process(????)

what I'm confused about is that I don't know if I have to consider
"clk" or "z" in sensitivity list or what? I have never used process so
far and all examples in books are only about one entity and one
process in them.

any suggestions will be apprecaited greatly.

thanks,
ak
Click to expand...

First of all you can't connect two ports from different entities in
deiffernet PROJECTs! both must be in the same project. Then, you can
have two entities or most simpler one entity and one process in it
containing both debouncer and counter. why don't you creat your
counter in the debouncer entity?!
is it the z signal you're trying to count? then creat your process
with 'clk' in the sensitivity list, and use 'z' as a clock enable
signal like the below structure:

mycounter:
process(clk)
begin
if rising_edge(clk) then
if z = '1' then
counter <= counter + '1';
end if;
end if;
end process;

But, after all, I think you should study VHDL a bit more, before
starting to write an HDL code.
good luck
 
On Oct 7, 10:25 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

First of all you can't connect two ports from different entities in
deiffernet PROJECTs!

Why?

--
Vince
Click to expand...
I meant by PROJECT here, an ISE or any other FPGA editor software. An
entitiy in a project can not be recognized or instantiated by
another(different) project. that's all! Note that it doesn't mean two
entities can't be connected through ports. it is easily done by
creating package for them, or using components and instatiating.
 
naliali a écrit:
On Oct 7, 10:25 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

First of all you can't connect two ports from different entities
in deiffernet PROJECTs!

Why?


I meant by PROJECT here, an ISE or any other FPGA editor software.
An entitiy in a project can not be recognized or instantiated by
another(different) project. that's all! Note that it doesn't mean
two entities can't be connected through ports. it is easily done by
creating package for them, or using components and instatiating.
Click to expand...
Ok, so your answer is software dependent...



--
Vince
 
On Oct 7, 1:23 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

On Oct 7, 10:25 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

First of all you can't connect two ports from different entities
in deiffernet PROJECTs!

Why?

I meant by PROJECT here, an ISE or any other FPGA editor software.
An entitiy in a project can not be recognized or instantiated by
another(different) project. that's all! Note that it doesn't mean
two entities can't be connected through ports. it is easily done by
creating package for them, or using components and instatiating.

Ok, so your answer is software dependent...

--
Vince
Click to expand...

Hello again,

thanks for the response:

this shouldn' be that hard I have no idea why I cannot find a sample
in book. See assume there is a debuncer and this debouncer clocks a
ring counter. I don't want to get in more details of the problem all
is just a debouncer and a ring counter:

_____________________________
| |
key(switch) -> | Debouncer | ->| d q | |
Clock -> | Debouncer | ------>| ring-counter qbar| --|



debouncer sends a clock to ring-counter and then the ouput of q goes
into a 3rd entity but its qbar or NOT(q) must go back to d (input of
ring-counter).

I hope now it makes sensse. HOW CAN I CREATE ALL THESE USING A SIGNAL?
ANY COMMENT?

thanks.
 
On Oct 7, 1:19 pm, Amit <amit.ko...@gmail.com> wrote:
On Oct 7, 1:23 am, Vince <debo...@free.fr> wrote:





naliali a écrit:

On Oct 7, 10:25 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

First of all you can't connect two ports from different entities
in deiffernet PROJECTs!

Why?

I meant by PROJECT here, an ISE or any other FPGA editor software.
An entitiy in a project can not be recognized or instantiated by
another(different) project. that's all! Note that it doesn't mean
two entities can't be connected through ports. it is easily done by
creating package for them, or using components and instatiating.

Ok, so your answer is software dependent...

--
Vince

Hello again,

thanks for the response:

this shouldn' be that hard I have no idea why I cannot find a sample
in book. See assume there is a debuncer and this debouncer clocks a
ring counter. I don't want to get in more details of the problem all
is just a debouncer and a ring counter:

_____________________________
| |
key(switch) -> | Debouncer | ->| d q | |
Clock -> | Debouncer | ------>| ring-counter qbar| --|

debouncer sends a clock to ring-counter and then the ouput of q goes
into a 3rd entity but its qbar or NOT(q) must go back to d (input of
ring-counter).

I hope now it makes sensse. HOW CAN I CREATE ALL THESE USING A SIGNAL?
ANY COMMENT?

thanks.- Hide quoted text -

- Show quoted text -
Click to expand...


naliali,

You had asked if the z signal I am trying to count? NO, ASSUME Z IS
THE OUTPUT OF THE DEBOUNCER. IT WILL CLOCK THE RING-COUNTER.
 
On Oct 7, 1:29 pm, Amit <amit.ko...@gmail.com> wrote:
On Oct 7, 1:19 pm, Amit <amit.ko...@gmail.com> wrote:





On Oct 7, 1:23 am, Vince <debo...@free.fr> wrote:

naliali a écrit:

On Oct 7, 10:25 am, Vince <debo...@free.fr> wrote:
naliali a écrit:

First of all you can't connect two ports from different entities
in deiffernet PROJECTs!

Why?

I meant by PROJECT here, an ISE or any other FPGA editor software.
An entitiy in a project can not be recognized or instantiated by
another(different) project. that's all! Note that it doesn't mean
two entities can't be connected through ports. it is easily done by
creating package for them, or using components and instatiating.

Ok, so your answer is software dependent...

--
Vince

Hello again,

thanks for the response:

this shouldn' be that hard I have no idea why I cannot find a sample
in book. See assume there is a debuncer and this debouncer clocks a
ring counter. I don't want to get in more details of the problem all
is just a debouncer and a ring counter:

_____________________________
| |
key(switch) -> | Debouncer | ->| d q | |
Clock -> | Debouncer | ------>| ring-counter qbar| --|

debouncer sends a clock to ring-counter and then the ouput of q goes
into a 3rd entity but its qbar or NOT(q) must go back to d (input of
ring-counter).

I hope now it makes sensse. HOW CAN I CREATE ALL THESE USING A SIGNAL?
ANY COMMENT?

thanks.- Hide quoted text -

- Show quoted text -

naliali,

You had asked if the z signal I am trying to count? NO, ASSUME Z IS
THE OUTPUT OF THE DEBOUNCER. IT WILL CLOCK THE RING-COUNTER.- Hide quoted text -

- Show quoted text -
Click to expand...

Forget it I will figure that out.

Thanks.
 
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