B
Brian Drummond
Guest
On Mon, 17 Dec 2012 08:28:08 +0100, Thomas Heller wrote:
single cycle (thanks to variable assignment!), delivering results several
cycles too early, and achieving a third of the intended performance!
- Brian
In my case it was cascading my carefully pipelined multiplications into aAm 15.12.2012 11:20, schrieb Brian Drummond:
On Tue, 11 Dec 2012 15:52:41 +0100, Thomas Heller wrote:
Here is the procedure:
procedure advance_state (
signal state : inout state_type;
constant next_state : in state_type;
signal counter : inout integer range 0 to 1000;
constant dt : in integer)
I have just re-tested with ISE14.3.
This bug is still there targeting Spartan-3 but goes away targeting S6.
I believe this may be the bug you are seeing...
Yes it seems this is the bug. Thanks for the confirmation!
single cycle (thanks to variable assignment!), delivering results several
cycles too early, and achieving a third of the intended performance!
- Brian