procedure overloading vs. ?

[yaveh (Yet Another Vhdl E]

Hi!

Can´t I overload a procedure and, depending on the type of parameter
passed do different things?

I works for different base types (e.g. boolean vs integer) but I can´t
get to compile this:


architecture sim of my_entity is
...

procedure one (
variable x : std_logic_vector(1 to 4)
) is
begin
....
end procedure;

procedure one (
variable x : std_logic_vector(1 to 8);
) is
begin
...
end procedure;

begin

...
end;

The tool complains about two bodies for the same subprogram or, in a
package declaration,
that a redefinition would happen...

Any workaround at hand?

(YAVEH) Yet Another Verification Engineer Hoping

 

[Andrew FPGA]

Can´t I overload a procedure and, depending on the type of parameter
passed do different things?

Do you really need two different procedures with same name? If the
functionality provided by the two procedures is different then I would
argue overloading is not the correct mechanism to use. If the two
procedures do different things, then rename the procedures to properly
reflect what each procedure does.

I use overloading when I have a set of functionality or processing I
want done, but the input(or output) data can be of different data
types.

If you just want to be able to handle std_logic_vectors of various
sizes then you can pass the slv in as an unconstrained array. e.g.
procedure blah( variable unconstrained_array : std_logic_vector ) is
begin ...

Then within the procedure you can do things like:

for i in unconstrained_array'range loop
--to access elements of the array use unconstrained_array(i)

unconstrained_array'length will give you the size of the array...

Regards
Andrew

 

[Andy]

Signature evaluation of multiple subprograms with the same name uses
argument types, not subtypes to differentiate them. So both bodies have
the same signature (std_logic_vector), and thus the error.

Write one subprogram with an unconstrained slv argument, and use the
'length to determine the behavior you want.

Andy


yaveh (Yet Another Vhdl Engineer Hoping) wrote:

Hi!

Can´t I overload a procedure and, depending on the type of parameter
passed do different things?

I works for different base types (e.g. boolean vs integer) but I can´t
get to compile this:


architecture sim of my_entity is
..

procedure one (
variable x : std_logic_vector(1 to 4)
) is
begin
...
end procedure;

procedure one (
variable x : std_logic_vector(1 to 8);
) is
begin
..
end procedure;

begin

..
end;

The tool complains about two bodies for the same subprogram or, in a
package declaration,
that a redefinition would happen...

Any workaround at hand?

(YAVEH) Yet Another Verification Engineer Hoping

 

[Paul Uiterlinden]

yaveh (Yet Another Vhdl Engineer Hoping) wrote:

Hi!

Can´t I overload a procedure and, depending on the type of parameter
passed do different things?

I works for different base types (e.g. boolean vs integer) but I
can´t get to compile this:


architecture sim of my_entity is
..

procedure one (
variable x : std_logic_vector(1 to 4)
) is
begin
...
end procedure;

procedure one (
variable x : std_logic_vector(1 to 8);
) is
begin
..
end procedure;

begin

..
end;

The tool complains about two bodies for the same subprogram or, in a
package declaration,
that a redefinition would happen...

As you already found out, this only works with different types.
std_logic_vector(1 to 4) and std_logic_vector(1 to 8) are not
different types.

Any workaround at hand?

Create just one subprogram with an unconstraint parameter and use the
length of the parameter to create the different behaviours.

procedure one (
variable x : std_logic_vector
) is
begin
case x'length is
when 4 =>
-- do something

when 8 =>
-- do something else

when others =>
report "Wrong length passed to procedure one"
severity failure;
end case;
end procedure;

(YAVEH) Yet Another Verification Engineer Hoping

hwgyn (hoping will get you nowhere)

--
Paul.
www.aimcom.nl
email address: switch x and s