Procedure Calls with variable number of Input Ports

[Analog_Guy]

I have posted before with this issue, but I still don't seem to
understand all the replies. I will provide my Procedure, which will
maybe shed some more light.

PROBLEM: I have a small device with a number of combinatorial
equations for which I need to create a testbench. My testbench
utilizes a package which contains all the relevant Procedures. I would
like my testbench to run through every combination of the n-input
equation and provide self-checking. I would also like to have 'one'
generic combinatorial procedure to handle any n-input equation.

TO DATE: Up to now, I can't figure out how to create a generic
procedure. I have created separate procedures to handle the 6-input
equations, 7-input equations, 8-input equations, etc. in my design.
This is very cumbersome.

EXAMPLE: Here is one of my Procedure call:
test_comb_6ip(tb, clk_int, "Test #1", 2, PORT_IN_1, PORT_IN_2,
PORT_IN_3, PORT_IN_4, PORT_IN_5, PORT_IN_6, PORT_OUT_2);

The PORT_IN_x signals are declared as INOUT since I both need to drive
as well as read for the self-checking Procedure.

Here are the Procedures:

-------------------------------------------------------------------------------
--
-- CHECK COMBINATORIAL 6-INPUT FUNCTIONALITY
-- =========================================
--
PROCEDURE check_comb_6ip ( VARIABLE tb : INOUT tb_rec;
CONSTANT TEST_TYPE : IN NATURAL;
SIGNAL dut_in_1, dut_in_2, dut_in_3,
dut_in_4, dut_in_5, dut_in_6 : INOUT STD_LOGIC;
SIGNAL dut_out : IN STD_LOGIC;
SIGNAL dut_out_stable : IN BOOLEAN) IS
--
VARIABLE logic_function : STD_LOGIC; -- Evaluate the desired logic
function based on the test type
--
BEGIN
IF (TEST_TYPE = 1) THEN
logic_function := NOT dut_in_1 OR NOT dut_in_2 OR dut_in_3 OR
dut_in_4 OR NOT dut_in_5 OR NOT dut_in_6; -- First valid 6-input
logic function
ELSIF (TEST_TYPE = 2) THEN
logic_function := NOT (NOT dut_in_1 OR NOT dut_in_2 OR dut_in_3 OR
dut_in_4 OR NOT dut_in_5 OR NOT dut_in_6); -- Second valid 6-input
logic function
ELSE
-- Terminate simulation for
an invalid test type
ASSERT (FALSE)
REPORT "Invalid logic function for 6-input combinatorial test."
SEVERITY FAILURE;
END IF;
--
IF ((dut_out = logic_function) AND dut_out_stable) THEN -- Check for
functional value that is stable
tb.test_passes := tb.test_passes + 1; -- PASS
condition
ELSE
tb.test_case_result := FALSE; -- Test Case
FAIL condition (reset at conclusion of test case)
tb.test_final_result := FALSE; -- Overall
FAIL condition (never reset)
END IF;
tb.test_total := tb.test_total + 1; -- Test
completed, increment test total
tb.test_case_result := TRUE; -- Clear test
case result for next test
END;
--
-------------------------------------------------------------------------------
--
-- COMBINATORIAL 6-INPUT FUNCTION TEST
-- ===================================
--
-- Test for 6-input combinatorial logic
--
-- Cycle through each valid combination of inputs, starting with 0 and
returning
-- to 0 after each valid input combination
--
--
PROCEDURE test_comb_6ip ( VARIABLE tb : INOUT tb_rec;
SIGNAL clock : IN STD_LOGIC;
text_in : IN STRING;
CONSTANT TEST_TYPE : IN NATURAL;
SIGNAL dut_in_1, dut_in_2, dut_in_3,
dut_in_4, dut_in_5, dut_in_6 : INOUT STD_LOGIC;
SIGNAL dut_out : IN STD_LOGIC) IS
--
VARIABLE test_counter : STD_LOGIC_VECTOR(SIX_IP_GATE_WIDTH - 1 DOWNTO
0) := (OTHERS => '0'); -- Test counter elements represent the DUT
inputs (i.e. counter width = number of inputs)

-- Set to minimum count
--
BEGIN
WAIT UNTIL (clock = '1' AND clock'EVENT); -- Synchronize
inputs to positive clock edge
FOR i IN 0 TO SIX_IP_GATE_DEPTH - 1 LOOP -- Cycle
through all 6-input logic combinations
dut_in_1 <= test_counter(SIX_IP_GATE_WIDTH - 1); -- Assign input
#1 to first (MSB) element of 'test_counter'
dut_in_2 <= test_counter(SIX_IP_GATE_WIDTH - 2); -- Assign input
#2 to second element of 'test_counter'
dut_in_3 <= test_counter(SIX_IP_GATE_WIDTH - 3); -- Assign input
#3 to third element of 'test_counter'
dut_in_4 <= test_counter(SIX_IP_GATE_WIDTH - 4); -- Assign input
#4 to fourth element of 'test_counter'
dut_in_5 <= test_counter(SIX_IP_GATE_WIDTH - 5); -- Assign input
#5 to fifth element of 'test_counter'
dut_in_6 <= test_counter(SIX_IP_GATE_WIDTH - 6); -- Assign input
#6 to sixth (LSB) element of 'test_counter'

check_comb_6ip(tb, TEST_TYPE, dut_in_1, dut_in_2, dut_in_3,
dut_in_4, dut_in_5, dut_in_6, dut_out); -- Test case verification

END LOOP;
END;
--
-------------------------------------------------------------------------------


HELP: I want one procedure whereby I can specify a variable number of
input PORTS, and use the 'RANGE or 'LENGTH within the Procedure to
figure out the unconstrained length.

I have tried aggregates, but it appears I need to create a new signal.
The new signal is assigned all the combinatorial values, but they are
not reflected in my input ports.

I have tried concatenation, but that doesn't work either.

I have been trying various things for a couple days now to no avail. I
would like to know if this type of thing can be done in VHDL???

 

[Mike Treseler]

Analog_Guy wrote:

I have posted before with this issue, but I still don't seem to
understand all the replies. I will provide my Procedure, which will
maybe shed some more light.

How about the process that calls the procedure?

PROBLEM: I have a small device with a number of combinatorial
equations for which I need to create a testbench.

Is this a glue logic application?
Is a 4 input gate the top level UUT?

My testbench
utilizes a package which contains all the relevant Procedures.

As a minimum, a testbench requires a null entity,
an architecture with at least one uut instance,
signal declarations for the wire harness
and one test process. I don't see any of this.
Procedures are icing on the cake. You need cake.

Here is a testbench example using procedures:
http://home.comcast.net/%7Emike_treseler/test_uart.vhd

Start out with a simple testbench for a single case
before you worry about abstractions for the general case.

-- Mike Treseler