Procedural assignment

[DW]

Are the following code extracts functionally equivalent and would the
synthesizer produce similar results? If not, why?

Example 1
=======
input a;
input b;
reg c;
wire a_and_b;
assign a_and_b = a & b;
always @(posedge clk)
c <= a_and_b;

Example 2
=======
input a;
input b;
reg c;
always @(posedge clk)
c <= a & b;

Thanks for reading...
DW

 

[Sathyanarayan B]

"DW" <dave_wooff@hotmail.com> wrote in message news:<c9n0u9$ihu$1$830fa7a5@news.demon.co.uk>...

Are the following code extracts functionally equivalent and would the
synthesizer produce similar results? If not, why?

Example 1
=======
input a;
input b;
reg c;
wire a_and_b;
assign a_and_b = a & b;
always @(posedge clk)
c <= a_and_b;

Example 2
=======
input a;
input b;
reg c;
always @(posedge clk)
c <= a & b;

Thanks for reading...
DW

Hi DW,
I dont see any reason why these 2 codes should not be equivalent. If
you have found it to be otherwise, please elaborate.

Satya

 

[DW]

"Sathyanarayan B" <satyanarayan_b@yahoo.com> wrote in message
news:65cb408c.0406080300.55a07c91@posting.google.com...

"DW" <dave_wooff@hotmail.com> wrote in message
news:<c9n0u9$ihu$1$830fa7a5@news.demon.co.uk>...
Are the following code extracts functionally equivalent and would the
synthesizer produce similar results? If not, why?

Example 1
=======
input a;
input b;
reg c;
wire a_and_b;
assign a_and_b = a & b;
always @(posedge clk)
c <= a_and_b;

Example 2
=======
input a;
input b;
reg c;
always @(posedge clk)
c <= a & b;

Thanks for reading...
DW

Hi DW,
I dont see any reason why these 2 codes should not be equivalent. If
you have found it to be otherwise, please elaborate.

Satya
Thanks, no I have not found this to be the case. I was just testing my

understanding.

 

[David Wooff]

--
Dave Wooff
dave@dmwooff.freeserve.co.uk
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message
news:m5mxc.16767$4S5.13573@attbi_s52...

DW wrote:

(snip)

assign a_and_b = a & b;
always @(posedge clk)
c <= a_and_b;

(snip)

always @(posedge clk)
c <= a & b;


I dont see any reason why these 2 codes should not be equivalent.
If you have found it to be otherwise, please elaborate.


Thanks, no I have not found this to be the case.
I was just testing my understanding.

I tend to think of continuous assignment (the assign command)
just like wiring parts together on a circuit board.

I believe it is possible that they will simulate differently,
as they might depend on the order of things that happen on the
same time step, but they should synthesize the same.

-- glen

Thankyou