procedural access to instance-arrays or generated instances?

Z

Zanan

Guest
I'm trying to figure out how to use a (initial) for-loop to access an
instance array.
But my simulator (Modelsim PE Student 6.2g) doesn't seem to allow
non-constant
index-value for either instance-arrays, or loop-generated instances!

Is there a way around this?

module my_xor(x, y, z );
input x;
input y;
output z;
assign z = y^x;
endmodule

module testbench;
genvar g;
generate for (g = 0; g < 2; g = g + 1 ) begin : aa
my_xor genxors( .x(), .y(), .z() ); // <-- my generate(d) instances
end
endgenerate

my_xor xors[1:0] (.x(), .y(), .z() ); // <-- my instance array!

integer i;
initial begin

for ( i = 0; i < 2; i = i + 1 )
$display( "xors[%0d].x = 1'b%b", xors.x ); // simulator error --
non-constant index to instance-array not allowed!

for ( i = 0; i < 2; i = i + 1 )
$display( "xors[%0d].x = 1'b%b", aa.genxors.x ); // simulator
error -- same complaint against generated-hierarchy!

#1 $finish;
end
endmodule
 
On Fri, 16 Mar 2007 05:14:58 GMT, "Zanan" <Zanon@nowhere.net> wrote:

I'm trying to figure out how to use a (initial) for-loop to access an
instance array.
But my simulator (Modelsim PE Student 6.2g) doesn't seem to allow
non-constant
index-value for either instance-arrays, or loop-generated instances!

Is there a way around this?
It's correct; you can't use a non-constant subscript in a hierarchical
reference of any kind in Verilog.

Instead, make the array of instances connect to an array of wires,
and then access that array using your variable subscript.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

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are not the views of Doulos Ltd., unless specifically stated.
 

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