Problems with Xilinx ISE6.1i P&Rs for Virtex II

S

Swarna B

Guest
Hi everybody,

I am having a problem with one of my designs on Virtex II.
I have been trying to get this working for quite some time now ( I
have generated around 50 BIT files by now) and have not yet got it :(
I have noticed that the BIT files I generate do not behave
consistently (most of the times it's working erroneously). i.e if I
make some small modification and regenerate the BIT file it goes
haywire. I am just sending out a constant data through a mux and some
registers. The data gets corrupted. This I observed by connecting the
outputs to a logic analyzer. I also am using ChipScope and I can see
that the data gets corrupted even as seen in ChipScope.
Currently I am suspecting things like -
- The DCM I have used to multiply an input clock by 2X. (I use the
multiplied clock all over the design.)
- My timing constraints, because, some of the corruptions I observed
hint at clock skew > Data delay.
- A high fanin MUX in the data path.

But ISE is not giving me any errors/warnings in this regards. It says
all constraints met as seen in the TWR file.

Is this a known issues of somekind! I can post more details(what?) if
somebody can analyze the specific nature of the problem.

Any information regarding this would be greatly helpful!

I looked through some of the older posts in this groups which talked
about clock jitter. One thing I have to do is - I have to look at my
input clock jitter spec. I definitely need more info :)

Thanks and Regards,
Swarna
 
"Swarna B" wrote:

I am having a problem with one of my designs on Virtex II.
....
I have noticed that the BIT files I generate do not behave
consistently (most of the times it's working erroneously).
....
- The DCM I have used to multiply an input clock by 2X. (I use the
multiplied clock all over the design.)
Click to expand...

What's the input frequency into the DCM?
Is the design fully synchronous?
How many clock domains? If more than one, how are you crossing them?
What's the source of the data this chip is processing?
Is there a reset tree? How is it designed?

More context would be useful.



--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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swarnakumar_ba@yahoo.com (Swarna B) wrote in message news:<11b5e6c5.0312230813.420bf400@posting.google.com>...
Hi everybody,

I am having a problem with one of my designs on Virtex II.
I have been trying to get this working for quite some time now ( I
have generated around 50 BIT files by now) and have not yet got it :(
I have noticed that the BIT files I generate do not behave
consistently (most of the times it's working erroneously). i.e if I
make some small modification and regenerate the BIT file it goes
haywire. I am just sending out a constant data through a mux and some
registers. The data gets corrupted. This I observed by connecting the
outputs to a logic analyzer. I also am using ChipScope and I can see
that the data gets corrupted even as seen in ChipScope.
Currently I am suspecting things like -
- The DCM I have used to multiply an input clock by 2X. (I use the
multiplied clock all over the design.)
- My timing constraints, because, some of the corruptions I observed
hint at clock skew > Data delay.
- A high fanin MUX in the data path.

But ISE is not giving me any errors/warnings in this regards. It says
all constraints met as seen in the TWR file.

Is this a known issues of somekind! I can post more details(what?) if
somebody can analyze the specific nature of the problem.

Any information regarding this would be greatly helpful!

I looked through some of the older posts in this groups which talked
about clock jitter. One thing I have to do is - I have to look at my
input clock jitter spec. I definitely need more info :)

Thanks and Regards,
Swarna
Click to expand...
1) Use one global clock buffer for all clock lines.

2) Next, if you still have problems , then use 2-phase clocking.

3) OR , add 2 nsec clock skew constraints on local clock lines.

Line delays can reach 20 nsecs on lines that have no time constraints.

4) Use the AREA Block constraint to locate logic in close areas to minimize

long routing path delays.

Bill Hanna
 
Hi Martin, Bill,
Thank you for the quick responses,
I have listed down some more details about the problem.

1. The DCM input clock is 40 MHz and hence the DCM would be in low
frequency mode.
2. I use the 2x output of the DCM to clock the data under
consideration, there are other clock domains in my design but I am not
crossing domains.
3. There is a host processor interface, this is asynchronous.
4. All the clocks are passed through global buffers, no local clocks
are used.
5. Just for trials I used the 40 MHz input clock directly, the problem
is gone. But if I use the 40MHz output (1x clock out) of the DCM the
problem is still there.

Thanks and regards,
Swarna

Here is the DCM I instantiated.
The input line CLKIN_IN is passed through a IBUFG before connecting to
this instant.

// Module ClockDouble
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST

module ClockDouble(
RST_IN,
LOCKED_OUT,
CLKIN_IN,
CLK2X_OUT,
CLK0_OUT
);

input RST_IN;
input CLKIN_IN;

output LOCKED_OUT;
output CLK2X_OUT;
output CLK0_OUT;

wire CLKFB_IN;
wire CLK0_BUF;
wire CLK2X_BUF;
wire CLKIN_IN_BUF;

DCM DCM_INST(
.CLKIN (CLKIN_IN),
.CLKFB (CLKFB_IN),
.RST (RST_IN),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSCLK (1'b0),
.DSSEN (1'b0),
.CLK0 (CLK0_BUF),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLKDV (),
.CLK2X (CLK2X_BUF),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.STATUS (),
.LOCKED (LOCKED_OUT),
.PSDONE ());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "2X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is 2
// synthesis attribute CLKFX_DIVIDE of DCM_INST is 1
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is 4
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is 25
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is
"SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute PHASE_SHIFT of DCM_INST is 0
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synthesis translate_off
defparam DCM_INST.CLK_FEEDBACK="2X";
defparam DCM_INST.CLKDV_DIVIDE=2;
defparam DCM_INST.CLKFX_DIVIDE=1;
defparam DCM_INST.CLKFX_MULTIPLY=4;
defparam DCM_INST.CLKIN_DIVIDE_BY_2="FALSE";
defparam DCM_INST.CLKIN_PERIOD=25;
defparam DCM_INST.CLKOUT_PHASE_SHIFT="NONE";
defparam DCM_INST.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE="LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE="LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION="TRUE";
defparam DCM_INST.PHASE_SHIFT=0;
defparam DCM_INST.STARTUP_WAIT="FALSE";
// synthesis translate_on

BUFG CLK0_BUFG_INST(
.I (CLK0_BUF),
.O (CLK0_OUT));

BUFG CLK2X_BUFG_INST(
.I (CLK2X_BUF),
.O (CLKFB_IN));

assign CLK2X_OUT = CLKFB_IN;

endmodule
 
Swarna B wrote:

5. Just for trials I used the 40 MHz input clock directly, the problem
is gone. But if I use the 40MHz output (1x clock out) of the DCM the
problem is still there.
Click to expand...
These symptoms indicate DCM is not asserting lock. Does your logic wait
until DCM achieves lock? DCM outputs are invalid and the output clock
freq. keeps on changing until DCM achieves lock. You should take into
consideration.

You may also want to try another alternate way of connecting the DCM
feedback. Instead of using clk2x as feedback, try using clk0 as feedback.
You need to modify the following in your code

// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
defparam DCM_INST.CLK_FEEDBACK="1X";

In DCM instantiation change

..CLKFB (CLK0_OUT),


Hope this helps !

Regards
Vikram
 
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