Problems with write-to-read in SRAM Controller

[ALuPin]

Hi,

at
http://mitglied.lycos.de/vazquez78
there are some plots to illustrate the following problem



As you can see the control sequence is WRITE READ NOP WRITE READ NOP ...

When I go from WRITE to READ
OE_n becomes active whereas WE_n becomes inactive at
the same time.

The simulation shows that the read data are not correct.

What does go wrong? Is the control sequence not right that is
asserting OE_n and deasserting WE_n at the same time is not allowed?

Thank you very much for your help.

Kind regards
Andrés V.


some portion of the Controller VHDL code
----------------------------------------

architecture xy of xyz is

....
begin

l_write_sram_enable <= (not l_we_bar) and (not l_cs_bar) and l_oe_bar;
Sram_data <= l_sram_data when l_write_sram_enable = '1' else (others => 'Z');

process(Reset, Clk) -- Clk=90MHz
begin
if Reset='1' then
....
elsif rising_edge(Clk) then
....
case l_state is

when write =>
OE_n <= '1'; -- SRAM control signals
CS_n <= '0';
WE_n <= '0';
ADDRESS <= ....; -- SRAM address
l_sram_data <= ...;
l_state <= read;

when read =>
OE_n <= '0';
CS_n <= '0';
WE_n <= '1';
ADDRESS <= ....;
l_state <= nop;


when nop =>
l_oe_bar <= '1';
l_cs_bar <= '1';
l_we_bar <= '1';
l_state <= write;
end if;

end process;

 

[Sandy]

Hi Andres,
It seems from ur code that the l_write_sram_enable is always '0' and hence
Sram_data is "ZZ.."
U have to reset l_we_bar..etc., somewhere.

-Sandy
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0404190657.5269998a@posting.google.com>...

Hi,

at
http://mitglied.lycos.de/vazquez78
there are some plots to illustrate the following problem



As you can see the control sequence is WRITE READ NOP WRITE READ NOP ...

When I go from WRITE to READ
OE_n becomes active whereas WE_n becomes inactive at
the same time.

The simulation shows that the read data are not correct.

What does go wrong? Is the control sequence not right that is
asserting OE_n and deasserting WE_n at the same time is not allowed?

Thank you very much for your help.

Kind regards
Andrés V.


some portion of the Controller VHDL code
----------------------------------------

architecture xy of xyz is

...
begin

l_write_sram_enable <= (not l_we_bar) and (not l_cs_bar) and l_oe_bar;
Sram_data <= l_sram_data when l_write_sram_enable = '1' else (others => 'Z');

process(Reset, Clk) -- Clk=90MHz
begin
if Reset='1' then
...
elsif rising_edge(Clk) then
...
case l_state is

when write =
OE_n <= '1'; -- SRAM control signals
CS_n <= '0';
WE_n <= '0';
ADDRESS <= ....; -- SRAM address
l_sram_data <= ...;
l_state <= read;

when read =
OE_n <= '0';
CS_n <= '0';
WE_n <= '1';
ADDRESS <= ....;
l_state <= nop;


when nop =
l_oe_bar <= '1';
l_cs_bar <= '1';
l_we_bar <= '1';
l_state <= write;
end if;

end process;

 

[ALuPin]

Sorry, some mistake of mine, of course l_we_bar, l_cs_bar, l_oe_bar
are not
the right names!
Please have a look at the corrected code.

architecture xy of xyz is

...
begin

l_write_sram_enable <= (not WE_n) and (not CS_n) and OE_n;
Sram_data <= l_sram_data when l_write_sram_enable = '1'
else (others => 'Z');

process(Reset, Clk) -- Clk=90MHz
begin
if Reset='1' then
...
elsif rising_edge(Clk) then
...
case l_state is

when write =>
OE_n <= '1'; -- SRAM control signals
CS_n <= '0';
WE_n <= '0';
ADDRESS <= ....; -- SRAM address
l_sram_data <= ...;
l_state <= read;

when read =>
OE_n <= '0';
CS_n <= '0';
WE_n <= '1';
ADDRESS <= ....;
l_state <= nop;


when nop =>
l_oe_bar <= '1';
l_cs_bar <= '1';
l_we_bar <= '1';
l_state <= write;
end if;

end process;

 

[ALuPin]

Hi,

please have a look at my homepage again.
I've put some additional colors in the plot to make it more clear.
Hope that helps to understand the problem.

I would appreciate your time and help.

Kind regards